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Yan Zhu

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Yan Zhu
諸嫣 Yan Zhu
Associate Professor
Phone: (+853) 8822-4418
Room Number: N21-4023c

For her citation of publications, please visit: https://scholar.google.com/citations?hl=en&user=fsX31qEAAAAJ

Academic Qualifications

  • Ph.D. in Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, China (2011)
  • M.Sc. in Electrical and Electronics Engineering, Faculty of Science and Technology, University of Macau, China (2008)
  • B.Sc. in Electrical Engineering and Automation, Shanghai University, Shanghai, China (2006)

Professional Experience

State-Key Laboratory of Analog and Mixed-Signal VLSI (AMSV)

  • Associate Professor, AMSV, University of Macau (July. 2019 – Present)
  • Assistant Professor, AMSV, University of Macau (2013 – Jun. 2019)
  • Post-doc Follow, AMSV, University of Macau (2012 –2013)

Others

  • Special Scientist, Dept. of EEE, University of California (2015)

Research

Research Interests

  • Analog and mixed-signal CMOS integrated circuits
  • RF direct sample ADC
  • mmW ADC
  • Phase ADC

Teaching Experience

B.Sc. Courses

  • Introduction of Data Converter (ECEB365)
  • Design Project (ECEB420)

M.Sc. Courses

  • Microelectronics for Telecommunication and Signal Processing (ECEN7009)
  • Thesis (ECEN7999)

Theses Supervision

Wang Wei 2016-2019 Design of Low-Power Mega to Hundred Mega Hz Bandwidth CTDSM
Xiaofeng Yang 2016-2019 Inductor-less Low Jitter Clock Circuit Techniques and Design Considerations
Dezhi Xing 2015-2018 Advanced Techniques in Analog to Digital Converters
WANG GUANCHENG 2014-2017 Split DAC mismatch calibration for SAR ADC
ZHANG WAI HONG 2015-2018 Background comparator offset calibration technique
HO IOK MENG 2015-2018 Multi-bit SAR switching techniques
LEI XUEWEI 2016-present Phase ADC
LI CHENG 2014-2018 SAR reference error analysis

 

Professional Services

Industrial Collaboration Coordinator, Institute of Microelectronics, University of Macau, 2019 – present

2015-present Reviewer: JSSC, TCAS I, TCAS II, TVLSI

Services at University of Macau

2014-present Stanley Ho East Asia College Affiliates

  1. Chi Hang Chan, Yan Zhu, Yan Lu, Sai Weng Sin, R. P. Martins, 2020 Macao Science & Technology Award – Technological Invention – 2nd Prize (Leading-Edge-Efficiency Data and Power Conversion Integrated Circuit Designs for Emerging Systems)

    The Science and Technology Development Fund(FDCT)

    Oct-2020
  2. Yan Lu, Man-Kay Law, Yan Zhu, Jun Yin, Chi Hang Chan, 2018 Macao Science & Technology Award – Technological Invention – 2nd Prize (Analog and Mixed-Signal Integrated Circuit Technologies Enabling a Smart Macau)

    The Science and Technology Development Fund(FDCT)

     Oct-2018
  3. Seng-Pan U, Yan Zhu, Sai Weng Sin, Chi Hang Chan, Technological Invention Award-Third Prize(High Performance Wideband Data Conversion Interfaces for a Evolving Informative World)

    The Science and Technology Development Fund(FDCT)

     Oct-2016
  4. Seng-Pan U, Sai Weng Sin, Yan Zhu, Chi Hang Chan, U-Fat Chio, Second-Class Award in the Technological Invention Award Category(Research and Development of Comprehensive and Advanced Data Conversion Platforms in Nanometer CMOS Technology)

    The Science and Technology Development Fund(FDCT)

     Nov-2014
  5. Yan Zhu, Scientific and Technological R&D Award (PhD Student), Macau Science and Technology Award 2012

    FDCT

     Oct-2012
  6. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Travel Grant Award (A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure)

    2012 IEEE Symposium on VLSI Circuits – VLSI 2012

     Jun-2012
  7. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, IEEE A-SSCC Student Design Contest Best Design Award (A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation)

    IEEE Asian Solid-State Circuits Conference

     Nov-2011
  1. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, Sampling front-end for analog to digital converter

    Granted Number: 8,947,283

    Application Number: 13/915,949

    US patent

     Feb-2015
  2. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, Analog to Digital Converter Circuit

    Granted Number: 201242261

    Application Number: 100107757

    Taiwan Patent

     Mar-2014
  3. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Cascade Analog to Digital Converting System

    Granted Number: 8,466,823

    Application Number: 13/198,856

    US Patent

     Jun-2013
  4. Sai Weng Sin, He Gong Wei, Li Ding, Yan Zhu, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption

    Granted Number: 8,427,355

    Application Number: 13/232,442

    US Patent

     Apr-2013
  5. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, N-Bits Successive Approximation Register Analog-to-Digital Converting System

    Granted Number: 8,344,931

    Application Number: 13/150,508

    US Patent

     Jan-2013
  1. Rui P. Martins; Pui-In Mak; Sai-Weng Sin; Man-Kay Law; Yan Zhu; Yan Lu; Jun Yin; Chi-Hang Chan; Yong Chen; Ka-Fai Un; Mo Huang; Minglei Zhang; Yang Jiang; Wei-Han Yu, Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications

    Foundations and Trends in Integrated Circuits and Systems

     Volume 1, Issue 2-3 Nov-2021
  2. Zihao Zheng; Lai Wei; Jorge Lagos; Ewout Martens; Yan Zhu; Chi-Hang Chan; Jan Craninckx; Rui P. Martins, A 3.3-GS/s 6-b Fully Dynamic Pipelined ADC With Linearized Dynamic Amplifier

    IEEE Journal of Solid-State Circuits

     Early Access Jul-2021
  3. Yan Song; Yan Zhu; Chi-Hang Chan; Rui P. Martins, A 40-MHz Bandwidth 75-dB SNDR Partial-Interleaving SAR-Assisted Noise-Shaping Pipeline ADC

    EEE Journal of Solid-State Circuits

     Vol.56, No.6. pp. 1772 -1783 Jun-2021
  4. Rui P. Martins, Pui-In Mak, Chi-Hang Chan, Jun Yin, Yan Zhu, Yong Chen, Yan Lu, Man-Kay Law, Sai-Weng Sin, Bird’s-eye view of Analog and Mixed-Signal Chips for the 21st Century

    International Journal of Circuit Theory and Applications

     vol. 49,No 3, pp. 746-761 Mar-2021
  5. Hong Shui Zhang, Yan Zhu, Chi Hang Chan, R. P Martins, A 25MHz-BW 75dB-SNDR Inherent Gain Error Tolerance Noise-Shaping SAR-Assisted Pipeline ADC with Background Offset Calibration Feb-2021
  6. Wei Wang, Chi Hang Chan, Yan Zhu, R. P. Martins, A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization

    IEEE Journal of Solid-State Circuits

     vol. 55, no. 6, pp. 1588-1598 Jun-2020
  7. Wenning Jiang, Yan Zhu, Chi Hang Chan, R. P. Martins, A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier

    IEEE Journal of Solid-State Circuits

     vol. 55, no. 2, pp. 322-332 Feb-2020
  8. Yan Song, Chi Hang Chan, Yan Zhu, R. P. Martins, A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC

    IEEE Journal of Solid-State Circuits

     vol. 55, no. 2, pp. 312-321 Feb-2020
  9. Xuewei Lei, Yan Zhu, Chi Hang Chan, R. P. Martins, A 4-b 7µW Phase Domain ADC With Time Domain Reference Generation for Low-Power FSK/PSK Demodulation

    IEEE Transactions on Circuits and Systems I: Regular Papers

     Vol. 66, No.9, pp. 3365-3372 Sep-2019
  10. Xiaofeng Yang, Chi Hang Chan, Yan Zhu, R. P. Martins, A -246dB Jitter-FoM 2.4GHz Calibration-Free RingOscillator PLL Achieving 9% Jitter Variation Over PVT Feb-2019
  11. Wenning Jiang, Yan Zhu, Minglei Zhang, Chi Hang Chan, R. P. Martins, A 7.6mW 1GS/s 60dB SNDR Single-Channel SARAssisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier Feb-2019
  12. Cheng Li, Chi Hang Chan, Yan Zhu, R. P. Martins, Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC

    IEEE Transactions on Circuits and Systems I: Regular Papers

     Vol.66, No.1, pp 82 - 93 Jan-2019
  13. Yan Zhu, Chi Hang Chan, Zi Hao Zheng, Cheng Li, Jianyu Zhong, R. P. Martins, A 0.19 mm² 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS

    IEEE Transactions on Circuits and Systems I: Regular Papers,

     pp 3606-3016 Nov-2018
  14. Wang GuanCheng, Cheng Li, Yan Zhu, Jianyu Zhong, Yan Lu, Chi Hang Chan, R. P. Martins, Missing-Code-Occurrence Probability Calibration Technique for DAC Nonlinearity With Supply and Reference Circuit Analysis in a SAR ADC

    IEEE Transactions on Circuits and Systems I: Regular Papers

     Vol.65, No.11, pp 3707 - 3719 Nov-2018
  15. Wang GuanCheng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     Vol. 26, No. 11, pp 2279 - 2289 Nov-2018
  16. Wei Wang, Yan Zhu, Chi Hang Chan, R. P. Martins, A 5.35-mW 10-MHz Single-Opamp Third-Order CTΔΣModulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS

    IEEE Journal of Solid-State Circuits

     Vol.53, no.10, pp 2783 - 2794 Oct-2018
  17. Yang Xiaofeng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology

    IEEE Transactions on Circuits and Systems I: Regular Papers

     vol.65, No.6, pp.1819-1829 Jun-2018
  18. Chi Hang Chan, Yan Zhu, Zhang WaiHong, Seng-Pan U, R. P. Martins, A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC with Background Offset Calibration

    IEEE Journal of Solid-State Circuits

     vol.53, No.3, pp.850-860 Mar-2018
  19. Yan Song, Chi Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, R. P. Martins, Passive Noise Shaping in SAR ADC With Improved Efficiency

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     Vol.26, Issue2, pp.416-420 Feb-2018
  20. Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu, Seng-Pan U, A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     vol. 26, no. 3, pp. 572-583 Dec-2017
  21. Chi Hang Chan, Yan Zhu, Cheng Li, Zhang WaiHong, Ho Iok Meng, Lai Wei, Seng-Pan U, R. P. Martins, 60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration

    IEEE Journal of Solid-State Circuits

     vol. 52, no. 10, pp. 2576-2588 Oct-2017
  22. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC

    in IEEE Transactions on Circuits and Systems I: Regular paper

     Vol.64, Issue 8, pp.1966-1976 Aug-2017
  23. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC

    IEEE Transactions on Circuits and Systems I: Regular paper

     Vol.64, No 7, pp.1684-1695 Jul-2017
  24. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     Vol.25, Issue 3, pp.1168-1172 Mar-2017
  25. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Boris Murmann, Seng-Pan U, R. P. Martins, Metastablility in SAR ADCs

    press in IEEE Transactions on CAS – Part II: Express Briefs

     Volume: 64, Issue: 2, pp.111 - 115 Feb-2017
  26. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations

    in IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     Vol: 25, Issue1, pp. 354-363 Jan-2017
  27. Yan Lu, Cheng Li, Yan Zhu, Mo Huang, Seng-Pan U, R. P. Martins, A 312 ps Response-Time LDO with Enhanced Super Source Follower in 28 nm CMOS

    Electronics Letters

     Volume: 52, Issue: 16, pp.1368 - 1370 Aug-2016
  28. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, An 11b 450 MS/s 3-way Time-Interleaved Sub-ranging Pipelined-SAR ADC in 65nm CMOS

    IEEE Journal of Solid-State Circuits

     Volume: 51, Issue: 5, pp. 1223 - 1234 May-2016
  29. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 6 b 5 GS/s 4 Interleaved 3 b/Cycle SAR ADC

    IEEE Journal of Solid-State Circuits

     vol. 51, Issue 2, pp. 365-377 Feb-2016
  30. Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     Issue 24, Issue 7, pp. 2603-2607 Jan-2016
  31. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Thermal and Reference Noise Analysis of Time-Interleaving SAR and Partial-Interleaving Pipelined-SAR ADCs

    IEEE Transactions on Circuits and Systems I: Regular Papers

     vol.62, no.9, pp.2196-2206 Sep-2015
  32. Yan Zhu, Chi Hang Chan, Wong, S.-S., Seng-Pan U, R. P. Martins, Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC

    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

     Volume:24 , Issue: 3, pp. 1203 - 1207 Jun-2015
  33. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Split-SAR ADCs: Improved Linearity with Power and Speed Optimization

    ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     Vol.22, Issue: 2 , pp 372 - 383 Feb-2014
  34. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

     vol.22, no.2, pp.372,383 Feb-2014
  35. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 5-Bit 1.25-GS/s 4x-Capacitive-Folding Flash ADC in 65-nm CMOS

    IEEE Journal of Solid-State Circuits

     Vol. 48, Issue 9, pp 2154-2169 Sep-2013
  36. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

    IEEE Journal of Solid-State Circuits

     Vol.48, Issue 8, pp 1783-1794 Aug-2013
  37. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

    IEEE Journal of Solid-State Circuits

     Vol.47, Issue 11, pp 2614-2626 Dec-2012
  38. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC

    IEEE Transactions on CAS – Part II: Express Briefs

     vol. 57, Issue 8, pp. 607-611 Aug-2010
  39. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS

    IEEE Journal of Solid-State Circuits

     vol. 45, Issue 6, pp. 1111-1121 Jun-2010
  40. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs

    Hindawi VLSI Design, Special Issue with "Selected Papers from the Midwest Symposium on Circuits and Systems

     vol. 2010, no. 1, pp. 1-8 Apr-2010
  41. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS

    IEEE Trans. on Circuits and System II – Express Briefs

     vol. 57, Issue 1, pp. 16-20 Jan-2010
  1. Junyan Hao, Minglei Zhang, Yanbo Zhang, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-Hang Chan and R. P. Martins, A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness

    2023 IEEE International Solid-State Circuits Conference (ISSCC)

     Feb-2023
  2. Yuefeng Cao, Minglei Zhang, Yan Zhu, Chi-Hang Chan and R. P. Martins, A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer

    2023 IEEE International Solid-State Circuits Conference (ISSCC)

     Feb-2023
  3. Hongshuai Zhang; Yan Zhu; Chi-Hang Chan; R. P. Martins, A 25MHz-BW 77.2dB-SNDR 2nd-Order Gain Error Shaping and NS Pipelined SAR ADC Based on Quantization-Prediction-Unrolled Scheme

    2023 IEEE International Solid-State Circuits Conference (ISSCC)

     Feb-2023
  4. Hongzhi Zhao, Minglei Zhang, Yan Zhu, Chi-Hang Chan and R. P. Martins, A 2×-Interleaved 9b 2.8GS/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input

    2023 IEEE International Solid-State Circuits Conference (ISSCC)

     Feb-2023
  5. Yanbo Zhang, Junyan Hao, Shubin Liu, Zhangming Zhu, Yan Zhu, Chi-hang Chan and R. P. Martins, A Single-channel 70dB-SNDR 100MHz-BW 4th-Order Noise-Shaping Pipeline SAR ADC with Residue Amplifier Error Shaping

    2023 IEEE International Solid-State Circuits Conference (ISSCC)

     Feb-2023
  6. Jiahao Liu; Yan Zhu; Chi Hang Chan; Rui Paulo Martins, A 0.46pJ/bit Ultralow-Power Entropy-Preselection-Based Strong PUF with Worst-Case BER<6.7×10-6

    2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), Session 11/ paper 11.3

     Nov-2021
  7. Lai Wei; Zihao Zheng; Nereo Markulic; Jorge Lagos; Ewout Martens; Yan Zhu; Chi-Hang Chan; Jan Craninckx; Rui Paulo Martins, An Auxiliary-Channel-Sharing Background Distortion and Gain CalibrationAchieving >8dB SFDR Improvement over 4th Nyquist Zone in 1GS/s ADC

    2021 Symposium on VLSI

     Jun-2021
  8. Kai Xing, Lei Wang, Yan Zhu, Chi Hang Chan, R. P. Martins, A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SABELD-Merged Integrator and 3-Stage Opamp

    2020 Symposia on VLSI Technology and Circuits

     Jun-2020
  9. Zihao Zheng, Lai Wei, Jorge Lagos, Ewout Martens, Yan Zhu, Chi Hang Chan, Jan Craninckx, R. P. Martins, A Single-Channel 5.5mW 3.3GS/s 6b Fully Dynamic Pipelined ADC with Post-Amplification Residue Generation

    IEEE International Solid-State Circuits Conference (ISSCC)

     pp. 254-256 Feb-2020
  10. Yan Song, Yan Zhu, Chi Hang Chan, R. P. Martins, A 2.56mW 40MHz-Bandwidth 75dB-SNDR PartialInterleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration

    IEEE International Solid-State Circuits Conference (ISSCC)

     pp.164-166 Feb-2020
  11. Minglei Zhang, Yan Zhu, Chi Hang Chan, R. P. Martins, A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input

    IEEE International Solid-State Circuits Conference (ISSCC)

     pp. 252-254 Feb-2020
  12. Wenning Jiang, Yan Zhu, Minglei Zhang, Chi Hang Chan, R. P. Martins, A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier

    IEEE International Solid-State Circuits Conference (ISSCC 2019

     pp.60-62 Feb-2019
  13. Minglei Zhang, Chi Hang Chan, Yan Zhu, R. P. Martins, A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques

    IEEE International Solid-State Circuits Conference (ISSCC 2019)

     pp.66-68 Feb-2019
  14. Wei Wang, Chi Hang Chan, Yan Zhu, R. P. Martins, A 72.6dB-SNDR 100MHz-BW 16.36mW CTDSM with Preliminary Sampling and Quantization Scheme in Backend Subranging QTZ

    IEEE International Solid-State Circuits Conference (ISSCC 2019)

     pp.340-342 Feb-2019
  15. Wenning Jiang, Yan Zhu, Chi Hang Chan, Boris Murmann, Seng-Pan U, R. P. Martins, A 7b 2 GS/s Time-Interleaved SAR ADC with Time Skew Calibration Based on Current Integrating Sampler

    2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)

     [Highlighted Paper] Nov-2018
  16. Chi Hang Chan, Yan Zhu, Zihao Zheng, R. P. Martins, A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end

    ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)

     Sep-2018
  17. Yan Song, Yan Zhu, Chi Hang Chan, Li Geng, R. P. Martins, A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure

    Proc. IEEE Symposium on VLSI Circuits - VLSI 2018

     Jun-2018
  18. Chi Hang Chan, Yan Zhu, Seng-Pan U, R. P. Martins, A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC

    forthcoming Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2018

     May-2018
  19. Yang Xiaofeng, Yan Zhu, Chi Hang Chan, Wang GuanCheng, Seng-Pan U, A 430frms 2.4GHz Ring-Oscillator PLL with Backend Discrete-Time Phase Noise Cancellation Achieving 240.5dB Jitter-FoM

    IEEE International Solid-State Circuits Conference (ISSCC 2018)

     [Student Research Preview] Feb-2018
  20. Wei Wang, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, A 5.35 mW 10 MHz Bandwidth CT Third-Order ∆∑ Modulator with Single Opamp Achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS

    IEEE Asian Solid-State Circuits Conference (A-SSCC)

     (highlighted paper and suggested to JSSC special issue), pp.285-288 Nov-2017
  21. Wang GuanCheng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC

    ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference

     Leuven, pp. 239-242. Sep-2017
  22. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Seng-Pan U, R. P. Martins, A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration

    IEEE International Solid-State Circuits Conference (ISSCC)

     pp. 282-284 Feb-2017
  23. Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Chon-Lam Lio, Seng-Pan U, R. P. Martins, A 0.011mm2 60dB SNDR 100MS/s Reference Error Calibrated SAR ADC with 3pF Decoupling Capacitance for Reference Voltages

    IEEE Asian Solid-State Circuits Conference (A-SSCC)

     pp. 145-148 (highlighted paper and invited to JSSC special issue) Nov-2016
  24. Lei Qiu, Kai Tang, Yan Zhu, Liter Siek, Yuanjin Zheng, Seng-Pan U, A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration

    IEEE Asian Solid-State Circuits Conference (A-SSCC)

     pp: 77 – 80 Nov-2016
  25. Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching

    IEEE ISCAS 2017

     accepted Oct-2016
  26. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction

    IEEE European Solid-State Circuits Conference – ESSCIRC 2016

     pp. 169-172 Sep-2016
  27. Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 12b 180MS/s 0.068mm2 Full-Calibration Integrated Pipelined-SAR ADC

    International Solid State Circuits Conference (ISSCC)

     Student Research Previews Feb-2015
  28. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 5.5mW 6b 5GS/S 4×-lnterleaved 3b/cycle SAR ADC in 65nm CMOS

    Solid- State Circuits Conference - (ISSCC)

     (Pre-doctoral achievement awards),pp1-3 Feb-2015
  29. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC

    IEEE European Solid-State Circuit Conference – (ESSCIRC)

     pp.211-214 Sep-2014
  30. Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, A 10.4-ENOB 120MS/s SAR ADC with DAC Linearity Calibration in 90nm CMOS

    IEEE Asian Solid-State Circuit Conference – (A-SSCC)

     pp 69-72 Nov-2013
  31. WenLan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS

    IEEE International Symposium on Circuits and Systems (ISCAS)

     pp 2239-2242 May-2013
  32. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC

    IEEE Asian Solid-State Circuit Conference – (A-SSCC)

     pp 153-156 Nov-2012
  33. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

    IEEE Custom Integrated Circuits Conference – CICC 2012

     pp 1-4 Aug-2012
  34. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC

    2012 Symposium on VLSI Circuits Digest of Technical Papers

     pp 90-91 Jun-2012
  35. Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure

    2012 Symposium on VLSI Circuits Digest of Technical Papers

     pp 86-87 Jun-2012
  36. Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

    Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic")

     pp. 61-64 Best Student Design Contest Award Nov-2011
  37. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

    Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic")

     pp. 233-236 Nov-2011
  38. Seng-Pan U, Sai Weng Sin, Yan Zhu, U-Fat Chio, He Gong Wei, R. P. Martins, Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs

    Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011

     pp. 173-176 Nov-2011
  39. Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC

    IEEE Midwest Symposium on Circuits and Systems – MWSCAS

     pp. 1-4 Aug-2011
  40. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H

    in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010

     pp. 218-221 Sep-2010
  41. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump

    IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010

     pp. 889-892 Aug-2010
  42. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs

    IEEE International Symposium on Circuits and Systems – ISCAS 2010

     pp. 607-611 May-2010
  43. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator

    in Proc. of 2009 International SoC Design Conference (ISOCC)

     pp. 392-395 Nov-2009
  44. Sai Weng Sin, He Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R. P. Martins, Franco Maloberti, On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator

    in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC)

     pp. 49-52 Nov-2009
  45. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Si-Seng Wong, Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs

    in Proc. of 2009 International SoC Design Conference (ISOCC)

     pp. 333-336 Nov-2009
  46. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Process- and Temperature- Insensitive Current-Controlled Delay Generator for Sampled-Data Systems

    in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

     pp. 1192-1195 Dec-2008
  47. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs

    in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

     pp. 1164-1167 Dec-2008
  48. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs

    in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2008

     pp. 642-645 Sep-2008
  49. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier

    ", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS)

     pp. 5-8 Aug-2008
  50. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

    in Proceedings of IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2008

     pp. 922-925 Aug-2008
  51. Minglei Zhang; Yan Zhu; Chi-Hang Chan; Rui P. Martins, A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration

    2021 Symposium on VLSI

     Jun-2021
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