U-Fat CHIO

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U-Fat CHIO
趙汝法 U-Fat CHIO
Year of Graduation: Mar 2012
Ph.D. Dissertation: Design Techniques for Low-Power High-Speed Analog-to-Digital Converters using Binary-Search and Subranging Schemes
Current Appointment: Associate Professor in Chongqing University of Posts and Telecommunications, Chongqing, China
  1. Seng-Pan U, Sai Weng Sin, Yan Zhu, Chi Hang Chan, U-Fat Chio, Second-Class Award in the Technological Invention Award Category(Research and Development of Comprehensive and Advanced Data Conversion Platforms in Nanometer CMOS Technology)

    The Science and Technology Development Fund(FDCT)

    Nov-2014
  2. U-Fat Chio, Scientific and Technological R&D Award (PhD Student), Macau Science and Technology Award 2012

    FDCT

    Oct-2012
  3. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Silk-Road Award (A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS)

    Digest of Technical Papers from IEEE International Solid-State Circuits Conference – ISSCC 2011

    [Awarded for best asian PhD student research in ISSCC (“World Chip Olympic”)] Feb-2011
  4. U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, Award for Research Excellence 2007-2009

    University of Macau

    Apr-2010
  5. U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, Bronze Leaf Certificate (Comparator-Based Successive Folding ADC)

    IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia 2009)

    Sep-2009
  1. Man-Chung Wong, Chi-Seng Lam, Yan-Zheng Yang, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu, Chi-Kong Wong, Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, Mixed signal controller

    Granted, No. 9,692,232

    US patent

    Jun-2017
  2. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, Analog to Digital Converter Circuit

    Granted Number: 201242261

    Application Number: 100107757

    Taiwan Patent

    Mar-2014
  3. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Delay Generator

    Granted Number: 201246793

    Application Number: 100116148

    Taiwan Patent

    Mar-2014
  4. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Cascade Analog to Digital Converting System

    Granted Number: 8,466,823

    Application Number: 13/198,856

    US Patent

    Jun-2013
  5. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Delay Generator

    Granted Number: 8,441,295

    Application Number: 13/289,229

    US Patent

    May-2013
  6. Sai Weng Sin, He Gong Wei, Li Ding, Yan Zhu, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, Franco Maloberti, A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption

    Granted Number: 8,427,355

    Application Number: 13/232,442

    US Patent

    Apr-2013
  7. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, N-Bits Successive Approximation Register Analog-to-Digital Converting System

    Granted Number: 8,344,931

    Application Number: 13/150,508

    US Patent

    Jan-2013
  1. Wen-Liang Zeng, Edoardo Bonizzoni, Chi-Wa U, Chi-Seng Lam, Sai-Weng Sin, U-Fat Chio, Franco Maloberti, Rui Paulo Martins, A SAR-ADC-Assisted DC-DC Converter with Fast Transient Recovery

    IEEE Transactions on Circuits and Systems II - Express Briefs (TCAS-II)

    Sep-2020
  2. U-Fat Chio, Kuo-Chih Wen, Sai Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, R. P. Martins, An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery

    IEEE Journal of Solid-State Circuits

    Vol.54, No.10, pp. 2637-2648 Oct-2019
  3. Man-Chung Wong, Yan-Zheng Yang, Chi-Seng Lam, Wai-Hei Choi, Ning-Yi Dai, Ya-jie Wu, Chi-Kong Wong, Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, Self-reconfiguration property of a mixed signal controller for improving power quality compensator during light loading

    IEEE Transactions on Power Electronics

    vol. 30, no. 10, pp. 5938 – 5951 Oct-2015
  4. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Split-SAR ADCs: Improved Linearity with Power and Speed Optimization

    ", IEEE Transactions on Very Large Scale Integration (VLSI) Systems

    Vol.22, Issue: 2 , pp 372 - 383 Feb-2014
  5. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

    Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

    vol.22, no.2, pp.372,383 Feb-2014
  6. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 2.3 mW 10-bit 170 MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

    IEEE Journal of Solid-State Circuits

    Vol.48, Issue 8, pp 1783-1794 Aug-2013
  7. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

    IEEE Journal of Solid-State Circuits

    Vol.47, no11, pp. 2763-2772 Nov-2012
  8. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Design and Experimental Verification of a Power Effective Flash-SAR Subranging ADC

    IEEE Transactions on CAS – Part II: Express Briefs

    vol. 57, Issue 8, pp. 607-611 Aug-2010
  9. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS

    IEEE Journal of Solid-State Circuits

    vol. 45, Issue 6, pp. 1111-1121 Jun-2010
  10. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Linearity Analysis On A Series-Split Capacitor Array for High-Speed SAR ADCs

    Hindawi VLSI Design, Special Issue with "Selected Papers from the Midwest Symposium on Circuits and Systems

    vol. 2010, no. 1, pp. 1-8 Apr-2010
  11. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Rapid Power-Switchable Track-and-Hold Amplifier in 90nm CMOS

    IEEE Trans. on Circuits and System II – Express Briefs

    vol. 57, Issue 1, pp. 16-20 Jan-2010
  12. Sai Weng Sin, U-Fat Chio, Seng-Pan U, R. P. Martins, Statistical Spectra and Distortion Analysis of Time-Interleaved Sampling Bandwidth Mismatch

    IEEE Trans. on Circuits and Systems II – Express Briefs

    vol. 55, Issue 7, pp. 648-652 Jul-2008
  1. U-Fat Chio, Kuo-Chih Wen, Sai Weng Sin, Chi-Seng Lam, Yan Lu, Franco Maloberti, R. P. Martins, An Integrated DC-DC Converter with Segmented Frequency Modulation and Multiphase Co-Work Control for Fast Transient Recovery

    2018 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    Nov-2018
  2. U-Fat Chio, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, A 5-bit 2 GS/s binary-search ADC with charge-steering comparators

    IEEE Asian Solid-State Circuits Conference (A-SSCC)

    pp221-224 Nov-2017
  3. Dante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U-Fat Chio, Sai Weng Sin, R. P. Martins, An 8-bit 0.7-GS/s Single Channel Flash-SAR ADC in 65-nm CMOS Technology

    . IEEE European Solid-State Circuits Conference – ESSCIRC 2016

    pp. 421-424 Sep-2016
  4. WenLan Wu, Yan Zhu, U-Fat Chio, Li Ding, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS

    IEEE International Symposium on Circuits and Systems (ISCAS)

    pp 2239-2242 May-2013
  5. Guohe Yin, He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS

    IEEE European Solid-State Circuits Conference – ESSCIRC 2012

    pp 377-380 Sep-2012
  6. Rui Wang, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique

    IEEE European Solid-State Circuits Conference – ESSCIRC 2012

    pp 265-268 Sep-2012
  7. Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

    IEEE Custom Integrated Circuits Conference – CICC 2012

    pp 1-4 Aug-2012
  8. Si-Seng Wong, U-Fat Chio, He Gong Wei, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators

    Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic")

    pp. 73-76 Nov-2011
  9. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

    Proceedings of IEEE Asian Solid-State Circuits Conference (A-SSCC, "Asia Chip Olympic")

    pp. 233-236 Nov-2011
  10. Seng-Pan U, Sai Weng Sin, Yan Zhu, U-Fat Chio, He Gong Wei, R. P. Martins, Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs

    Proc. of IEEE International Symposium on Radio-Frequency Integration Technology – RFIT’2011

    pp. 173-176 Nov-2011
  11. Bo Sun, U-Fat Chio, Chi-Seng Lam, Ning-Yi Dai, Man-Chung Wong, Chi-Kong Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, A FPGA-Based Power Electronics Controller for Hybrid Active Power Filters

    IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia)

    Macao, China, pp. 25-28 Oct-2011
  12. Rui Wang, U-Fat Chio, Chi Hang Chan, Li Ding, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A time-efficient dither-injection scheme for pipelined SAR ADC

    IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia)

    pp. 9-12 Oct-2011
  13. U-Fat Chio, Chi Hang Chan, Hou-Lon Choi, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 7-bit 300-MS/s Subranging ADC with Embedded Threshold & Gain-Loss Calibration

    ", IEEE European Solid-State Circuits Conference – ESSCIRC 2011

    pp. 363-366 Sep-2011
  14. Bo Sun, Ning-Yi Dai, U-Fat Chio, Man-Chung Wong, Chi-Kong Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, FPGA-based Decoupled Double Synchronous Reference Frame PLL for Active Power Filters

    2011 6th IEEE Conference on Industrial Electronics and Applications (ICIEA)

    pp. 2145 – 2150 Jun-2011
  15. He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS

    IEEE International Solid-State Circuit Conference (ISSCC),

    pp. 188-189 Feb-2011
  16. Guohe Yin, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications

    IEEE International Conference on Electronics, Circuits and Systems (ICECS)

    pp. 878-881 Dec-2010
  17. He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation

    IEEE Asian Solid-State Circuits Conference – ASSCC 2010

    pp. 1-4 Nov-2010
  18. Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H

    in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010

    pp. 218-221 Sep-2010
  19. Si-Seng Wong, U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power Effective 5-bit 600 MS/s Binary-Search ADC with Simplified Switching

    in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010

    pp. 29-32 Aug-2010
  20. Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Threshold-Embedded Offset Calibration Technique for Inverter-Based Flash ADCs

    in Proc. IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010

    pp. 489-492 Aug-2010
  21. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Parasitics Nonlinearity Cancellation Technique for Split DAC Architecture by Using Capacitive Charge-Pump

    IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2010

    pp. 889-892 Aug-2010
  22. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Voltage Feedback Charge Compensation Technique for Split DAC Architecture in SAR ADCs

    IEEE International Symposium on Circuits and Systems – ISCAS 2010

    pp. 607-611 May-2010
  23. Chi Hang Chan, Yan Zhu, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator

    in Proc. of 2009 International SoC Design Conference (ISOCC)

    pp. 392-395 Nov-2009
  24. Sai Weng Sin, He Gong Wei, U-Fat Chio, Yan Zhu, Seng-Pan U, R. P. Martins, Franco Maloberti, On-Chip Small Capacitor Mismatches Measurement Technique using Beta-Multiplier-Biased Ring Oscillator

    in Proc. of 2009 IEEE Asian Solid-State Circuit Conference (A-SSCC)

    pp. 49-52 Nov-2009
  25. Yan Zhu, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Si-Seng Wong, Parasitic Calibration by Two-Step Ratio Approaching Techinque for Split Capacitor Array SAR ADCs

    in Proc. of 2009 International SoC Design Conference (ISOCC)

    pp. 333-336 Nov-2009
  26. U-Fat Chio, Hou-Lon Choi, Chi Hang Chan, Si-Seng Wong, Sai Weng Sin, Seng-Pan U, R. P. Martins, Comparator-Based Successive Folding ADC

    IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

    pp. 117-120 Jan-2009
  27. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Process- and Temperature- Insensitive Current-Controlled Delay Generator for Sampled-Data Systems

    in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

    pp. 1192-1195 Dec-2008
  28. U-Fat Chio, He Gong Wei, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Self-Timing Switch-Driving Register by Precharge-Evaluate Logic for High-Speed SAR ADCs

    in Proc. of IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

    pp. 1164-1167 Dec-2008
  29. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power-Efficient Capacitor Structure for High-Speed Charge Recycling SAR ADCs

    in Proceedings of IEEE International Conference on Electronics, Circuits, and Systems - ICECS 2008

    pp. 642-645 Sep-2008
  30. He Gong Wei, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power Scalable 6-bit 1.2GS/s Flash ADC with Power on/off Track-and-Hold and Preamplifier

    ", in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS)

    pp. 5-8 Aug-2008
  31. Yan Zhu, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

    in Proceedings of IEEE International Midwest Symposium on Circuits and Systems – MWSCAS 2008

    pp. 922-925 Aug-2008
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