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Zushu YAN

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Zushu YAN
嚴祖樹 Zushu YAN
Year of Graduation: Jul 2014
Ph.D. Dissertation: Systematic design and implementation of single-stage and multi-stage CMOS amplifiers
Current Appointment: Senior Design Engineer at Marvell, San Clara, California, USA
  1. Zushu Yan, IEEE Solid-State Circuits Society Predoctoral Achievement Award 2013-14

    IEEE Solid-State Circuits Society

     Feb-2014
  2. Zushu Yan, Scientific and Technological R&D Award (PhD Student), Macau Science and Technology Award 2012

    FDCT

     Oct-2012
  1. Zushu Yan, Pui In Mak, Man-Kay Law, R. P. Martins, Frequency Compensation Techniques for Low-Power and Small-Area Multistage Amplifiers

    Granted Number: 8,963,639

    Application Number: 13/770,020

    US Patent

     Feb-2015
  1. Zushu Yan, Pui In Mak, Man-Kay Law, R. P. Martins, Franco Maloberti, Nested-Current-Mirror Rail-to-Rail-Output Single-Stage Amplifier With Enhancements of DC Gain, GBW and Slew Rate

    IEEE Journal of Solid-State Circuits

     vol. 50, pp. 2353-2366 Oct-2015
  2. Zushu Yan, Wei Wang, Pui In Mak, Man-Kay Law, R. P. Martins, A 0.0045-mm2 32.4-µW Two-Stage Amplifier for pF-to-nF Load Using CM Frequency Compensation

    IEEE Transactions on Circuits and Systems – II

     vol. 62, pp. 246-250 Mar-2015
  3. Zushu Yan, Pui In Mak, Man-Kay Law, R. P. Martins, 0.0045mm2 15.8μW Three-Stage Amplifier Driving 10x-Wide (0.15 to 1.5nF) Capacitive Loads with >50° Phase Margin

    IET Electronics Letters

     vol. 51, pp. 454-456 Mar-2015
  4. Zushu Yan, Pui In Mak, Man-Kay Law, R. P. Martins, A 0.016-mm2 144-µW Three-Stage Amplifier Capable of Driving 1-to-15 nF Capacitive Load with >0.95-MHz GBW

    IEEE Journal of Solid-State Circuits

     Vol.48, Issue 2 , pp 527-540 Feb-2013
  5. Zushu Yan, Pui In Mak, Man-Kay Law, R. P. Martins, Ultra-area-efficient three-stage amplifier using current buffer Miller compensation and parallel compensation

    Electronics Letters

     Vol.48, Issue 11, pp 624-626 May-2012
  6. Zushu Yan, Pui In Mak, R. P. Martins, Double Recycling Technique for Folded-Cascode OTA

    Analog Integrated Circuits and Signal Processing, Springer

     Vol. 71, Issue 1, pp 137-141 Apr-2012
  7. Zushu Yan, Pui In Mak, R. P. Martins, Two-Stage Operational Amplifiers: Power-and-Area-Efficient Frequency Compensation for Driving a Wide Range of Capacitive Load

    Circuits and Systems Magazine, IEEE

     Vol.11 , Issue: 1 Mar-2011
  1. Wei Wang, Zushu Yan, Pui In Mak, Man-Kay Law, R. P. Martins, Micropower Two-Stage Amplifier Employing Recycling Current-Buffer Miller Compensation

    IEEE Int. Symp. on Circuits and Systems (ISCAS)

     pp. 1889-1892 Jun-2014
  2. Zushu Yan, Pui In Mak, Man-Kay Law, R. P. Martins, Franco Maloberti, A 0.0013mm2 3.6μW Nested-Current-Mirror Single-Stage Amplifier Driving 0.15-to-15nF Capacitive Loads with >62° Phase Margin

    IEEE International Solid-State Circuits Conference (ISSCC)

     pp. 288-289 Feb-2014
  3. Zushu Yan, Pui In Mak, Man-Kay Law, R. P. Martins, 0.0064mm2 12.6µW Three-Stage Amplifier with 1.38MHz GBW at 1nF Capacitive Load

    International Solid-State Circuits Conference, ISSCC 2013 (SRP)

     Feb-2013
  4. Zushu Yan, Pui In Mak, Man-Kay Law, R. P. Martins, A 0.016mm2 144µW Three-Stage Amplifier Capable of Driving 1-to-15nF Capacitive Load with >0.95MHz GBW

    Digest of Technical Papers from IEEE International Solid-State Circuits Conference (ISSCC 2012, "World Chip Olympic")

     pp 368-369 Feb-2012
  5. Miao Liu, Pui In Mak, Zushu Yan, R. P. Martins, A High-Voltage-Enabled Recycling Folded Cascode OpAmp for Nanoscale CMOS Technologies

    IEEE International Symposium on Circuits and Systems (ISCAS)

     pp. 33-36 May-2011
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