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Yang Jiang

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Yang Jiang
江洋 Yang Jiang
Assistant Professor
Current Appointment:
Phone: (+853) 8822-9939
Room Number: N21-4027e

Academic Qualifications

  • Ph.D. in Electrical and Computer Engineering, Faculty of Science and Technology, University of Macau, China (2019)
  • M.Sc. in Electrical and Electronics Engineering, Faculty of Science and Technology, University of Macau, China (2012)
  • B.Sc. in Electrical and Electronics Engineering, Faculty of Science and Technology, University of Macau, China (2009)

Professional Experience

      State-Key Laboratory of Analog and Mixed-Signal VLSI (AMSV)

  • Assistant Professor, AMSV, University of Macau (Feb. 2021 –)
  • Research Assistant Professor, AMSV, University of Macau (Sep. 2019 – Feb. 2021)
  • Postdoctoral Follow, AMSV, University of Macau (Apr. 2019 – Sep. 2019)

      Others

  • Visiting Associate Research Fellow, the University of Tokyo, Japan (Jan. 2020 – Jul. 2020)

Research

Research Interests

  • Integrated Power Converters
  • Integrated Device Drivers
  • Energy Harvesting Interface

Teaching Experience

M.Sc. Courses

  • New postgraduate courses to be open in 2021 fall

Funded Projects

  • ​High-performance on-chip DC-DC converter design for future portable IoT devices
    (PI, funded by University of Macau, Multi-Year Research Grant (MYRG) 2022-23)

Professional Affiliations

  • Member of Power and Energy Circuits and Systems Technical Committee (PECAS), IEEE CASS
  • Member of IEEE Solid-State Circuits Society (SSCS)
  • Member of IEEE Circuits and Systems Society (CASS)

Professional Services

  • Technical Program Committee Member of IEEE International Conf. on Electronics, Circuits and Systems (ICECS), 2020.
  • Review Committee Member of IEEE Asia Pacific Conf. on Circuits and Systems (APCCAS), 2019.
  • Peer Reviewer of
    IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
    IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
    IEEE Access
    Microelectronics Journal
    IEICE Electronics Express
    IEEE International Symposium on Circuits and Systems (ISCAS)
    IEEE International Conference on Electronics Circuits and Systems (ICECS)
    IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
    IEEE Biomedical Circuits and Systems Conference (BioCAS)
    IEEE Asia Symposium on Quality Electronic Design (ASQED)
  1. Yang Jiang, Xiaofeng Yu, ChenYan Cai, Third Prize for the Final Year Project Supervised (A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers)

    “Challenge Cup” National Intervarsity Science and Technology Competition

     Nov-2009
  2. Yang Jiang, Xiaofeng Yu, ChenYan Cai, Champion for the Final Year Project Supervised (A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers)

    2009 IEEE Project Competitions

     Sep-2009
  3. Yang Jiang, Xiaofeng Yu, ChenYan Cai, 3rd Class Award (A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers)

    The Challenging Cup (挑戰盃) China National University Students Project Competition

     Apr-2009
  4. Yang Jiang, Scientific and Technological R&D Award for Postgraduates

    The Science and Technology Development Fund (FDCT)

     Jan-2020
  5. Yang Jiang, Pre-Doctoral Achievement Award

    IEEE Solid-State Circuits Society

     Jan-2019
  6. Yang Jiang , Synopsys Academic Prize

    University of Macau

     Jan-2019
  1. Jiangchao Wu, Ka-Chon Lei, Hou-Man Leong, *Yang Jiang, Man-Kay Law, Pui In Mak, R. P. Martins (*Corresponding Author), Fully Integrated High Voltage Pulse Driver Using Switched-Capacitor Voltage Multiplier and Synchronous Charge Compensation in 65-nm CMOS

    IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), Vol. 66, Issue 10

     Oct-2019
  2. Yang Jiang, Man-Kay Law, Pui In Mak, R. P. Martins, Algorithmic Voltage-Feed-In Topology for Fully Integrated Fine-Grained Rational Buck–Boost Switched-Capacitor DC–DC Converters

    IEEE Journal of Solid-State Circuits

     Vol.53, No.12, pp 3455 - 3469 [Invited Paper] Dec-2018
  3. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters

    Analog Integrated Circuits and Signal Processing, Springer

     Vol.76, Issue1, pp 35-46 Jul-2013
  4. Xin Lu, Man-Kay Law, Yang Jiang, Xiaojin Zhao, Pui-In Mak, and Rui P. Martins, A 4-μm Diameter SPAD Using Less-Doped N-Well Guard Ring in Baseline 65-nm CMOS

    IEEE Transactions on Electron Devices (TED)

     Vol 67. Issue 5, 2020. May-2020
  5. Yang Jiang, Man-Kay Law, Zhiyuan Chen, Pui-In Mak, and Rui P. Martins, Algebraic Series-Parallel-Based Switched-Capacitor DC-DC Boost Converter with Wide Input Voltage Range and Enhanced Power Density

    IEEE Journal of Solid-State Circuits (JSSC)

     Vol. 54, Issue 11 Nov-2019
  1. Zhiyuan Chen, Yang Jiang, Man-Kay Law, Pui In Mak, Xiaoyang Zeng, R. P. Martins, A Piezoelectric Energy-Harvesting Interface Using Split-Phase Flipping-Capacitor Rectifier and Capacitor Reuse Multiple-VCR SC DC-DC Achieving 9.3× Energy-Extraction Improvement

    IEEE International Solid-State Circuits Conference (ISSCC 2019)

     pp. 424-426 Feb-2019
  2. JIANG Yang, Man-Kay Law, Pui In Mak, R. P. Martins, A 0.22-to-2.4V-Input Fine-Grained Fully-Integrated Rational Buck-Boost SC DC-DC Converter Using Algorithmic Voltage-Feed-In (AVFI) Topology Archiving 84.1% Peak Efficiency at 13.2μW/mm2

    IEEE Int. Solid-State Circuit Conference (ISSCC), Digest of Technical Papers

     accepted and [Invited Special Issue in JSSC], pp. 422-423 Feb-2018
  3. Biao Chen, JIANG Yang, Kwan-Ting Ng, Man-Kay Law, Pui In Mak, R. P. Martins, A Wide Range High Efficiency Fully Integrated Switched-Capacitor DC-DC Converter with Fixed Output Spectrum Modulation

    IEEE Int. Conference of Electron Devices and Solid-State Circuits (EDSSC)

     Oct-2017
  4. Yan Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Continuous-Time VCO-Assisted VCO-Based Sigma Delta Modulator with 76.6dB SNDR and 10MHz BW

    IEEE International Symposium on Circuits and Systems (ISCAS)

     pp 373-376 May-2013
  5. Yun Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators

    IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

     pp 29-32 Dec-2012
  6. Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity

    IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

     pp 33-36 Dec-2012
  7. Zhijie Chen, Yang Jiang, ChenYan Cai, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application

    IEEE Asian Solid-State Circuit Conference – (A-SSCC)

     pp 257-260 Nov-2012
  8. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators

    IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2012

     pp 1096-1099 Aug-2012
  9. Tao He, Yang Jiang, Yun Du, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer

    IEEE Int. Symposium on Circuits and Systems (ISCAS)

     pp 65-69 May-2012
  10. JIANG Yang, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC

    IEEE Midwest Symposium on Circuits and Systems – MWSCAS

     pp. 1-4 Aug-2011
  11. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time Sigma-Delta Modulators

    IEEE Midwest Symposium on Circuits and Systems – MWSCAS

     pp. 1-4 Aug-2011
  12. Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range

    IEEE International Midwest Symposium on Circuits and Systems – MWSCAS

     pp. 1-4 Aug-2011
  13. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators

    IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

     pp. 1011-1014 Dec-2010
  14. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators

    IEEE International Conference on Electronics, Circuits and Systems (ICECS

     pp. 547-550 Dec-2010
  15. Jinwei Zhao, Yang Jiang, Man-Kay Law, Rami Ghannam, Muhammad Imran, Hadi Heidari, An Implantable Photovoltaic Energy Harvesting System with Skin Optical Analysis

    IEEE International Conference on Electronics Circuits and Systems (ICECS)

     Nov-2020
  16. Yang Jiang, Pui-In Mak, Rui Martins, Man-Kay Law, ISSCC – Student Research Preview (SRP) Feb-2017
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