Data Conversion and Signal Processing

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Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, A 550μW 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS

Proc. IEEE Symposium on VLSI Circuits - VLSI 2018

Jun-2018
Chi Hang Chan, Yan Zhu, Seng-Pan U, R. P. Martins, A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC

forthcoming Proc. IEEE International Symposium on Circuits and Systems – ISCAS 2018

May-2018
Chi Hang Chan, Yan Zhu, Zhang WaiHong, Seng-Pan U, R. P. Martins, A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC with Background Offset Calibration

IEEE Journal of Solid-State Circuits

vol.53, No.3, pp.850-860 Mar-2018
Yang Xiaofeng, Yan Zhu, Chi Hang Chan, Wang GuanCheng, Seng-Pan U, A 430frms 2.4GHz Ring-Oscillator PLL with Backend Discrete-Time Phase Noise Cancellation Achieving 240.5dB Jitter-FoM

IEEE International Solid-State Circuits Conference (ISSCC 2018)

[Student Research Preview] Feb-2018
Yan Song, Chi Hang Chan, Yan Zhu, Li Geng, Seng-Pan U, R. P. Martins, Passive Noise Shaping in SAR ADC With Improved Efficiency

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Vol.26, Issue2, pp.416-420 Feb-2018
Weiwei Qin, Sai Weng Sin, Seng-Pan U, R. P. Martins, Quick and Cost-Efficient A/D Converter Static Characterization using Low-Precision Testing Signal

Microelectronics Journal - Elsevier

vol. 74, pp.86-93 Feb-2018
Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek, Yan Zhu, Seng-Pan U, A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

vol. 26, no. 3, pp. 572-583 Dec-2017
Wang GuanCheng, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC

ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference

Leuven, pp. 239-242. Sep-2017
Wei Wang, Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, A 5.35 mW 10 MHz Bandwidth CT Third-Order ∆∑ Modulator with Single Opamp Achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS

IEEE Asian Solid-State Circuits Conference (A-SSCC)

(highlighted paper and suggested to JSSC special issue), pp.285-288 Nov-2017
Lei Qiu, Kai Tang, Yan Zhu, Liter Siek, Yuanjin Zheng, Seng-Pan U, A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration

IEEE Asian Solid-State Circuits Conference (A-SSCC)

pp: 77 – 80 Nov-2016
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