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ChenYan Cai

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ChenYan Cai
蔡辰燕 ChenYan Cai
Research Assistant
  1. Chen Yan Cai , Scientific and Technological R&D Award (Master Student), Macau Science and Technology Award 2014

    FDCT

     Jul-2014
  1. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, Excess-loop-delay compensation technique for CT ΔΣ modulator with hybrid active-passive loop-filters

    Analog Integrated Circuits and Signal Processing, Springer

     Vol.76, Issue1, pp 35-46 Jul-2013
  2. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, Excess-Loop-Delay Compensation Technique for CT Delta Sigma Modulator with Hybrid Active-Passive Loop-Filters

    Analog Integrated Circuits and Signal Processing, Vol. 76, Issue 1

     May-2013
  1. Zhijie Chen, Yang Jiang, ChenYan Cai, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application

    IEEE Asian Solid-State Circuit Conference – (A-SSCC)

     pp 257-260 Nov-2012
  2. Zhijie Chen, JIANG Yang, Chenyan Cai, He-Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application

    in IEEE Asian Solid State Circuits Conference (A-SSCC)

     Nov-2012
  3. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators

    IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2012

     pp 1096-1099 Aug-2012
  4. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators

    in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

     Aug-2012
  5. JIANG Yang, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC

    IEEE Midwest Symposium on Circuits and Systems – MWSCAS

     pp. 1-4 Aug-2011
  6. ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time Sigma-Delta Modulators

    IEEE Midwest Symposium on Circuits and Systems – MWSCAS

     pp. 1-4 Aug-2011
  7. Chenyan Cai, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Passive Excess-Loop-Delay Compensation Technique for Gm-C Based Continuous-Time ΣΔ Modulators

    in IEEE International Midwest Symposium on Circuits and Systems (MWSCAS)

     Aug-2011
  8. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators

    IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

     pp. 1011-1014 Dec-2010
  9. Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators

    IEEE International Conference on Electronics, Circuits and Systems (ICECS

     pp. 547-550 Dec-2010
  10. JIANG Yang, Kim Fai Wong, Chenyan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators

    in IEEE International Conference on Electronics, Circuits and Systems (ICECS)

     pp.547-550 Dec-2010
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