Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC
2019 Aug 01 | Thu
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A 0.19 mm² 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS
2019 Aug 01 | Thu
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Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area
2019 Aug 01 | Thu
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A 10-MHz Bandwidth Two-Path Third-OrderΣΔModulator With Cross-Coupling Branches
2019 Aug 01 | Thu
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A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current
2019 Aug 01 | Thu
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