Data Conversion and Signal Processing

A 550μW 20kHz BW 100.8dB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65nm CMOS

2018 Sep 06 | Thu

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A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC

2018 Sep 06 | Thu

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A 14-bit Split Pipeline ADC with Self-Adjusted Opamp-Sharing Duty Cycle

2018 Sep 06 | Thu

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A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC with Background Offset Calibration

2018 Sep 06 | Thu

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Quick and Cost-Efficient A/D Converter Static Characterization using Low-Precision Testing Signal

2018 Sep 06 | Thu

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A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure

2018 Sep 06 | Thu

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A 39mW 7b 8GS/s 8-way TI ADC with Cross-linearized Input and Bootstrapped Sampling Buffer Front-end

2018 Sep 01 | Sat

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Analysis of Common-Mode Interference and Jitter of Clock Receiver Circuits With Improved Topology

2018 Jun 01 | Fri

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A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ΣΔ ADC Based on the Pipelined-SAR Structure

2018 Jun 01 | Fri

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A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS

2018 Jun 01 | Fri

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