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Zunsong Yang

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Zunsong Yang
Zunsong Yang
  1. Zunsong Yang, Yong Chen, Pui-In Mak, Rui P. Martins, A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS

    IEEE Transactions on Circuits and Systems I: Regular Papers

     vol. 68, No.6, pp. 2307-2316 Jun-2021
  2. Zunsong Yang, Yong Chen, Jia Yuan, Pui-In Mak, and Rui P. Martins, A 3.3-GHz Integer-N Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM

    IEEE Transactions on VLSI systems

     vol. 30, pp. 238–242 Feb-2021
  3. Zunsong Yang, Yong Chen, Shiheng Yang, Pui In Mak, R. P. Martins, A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector

    IEEE Access

     vol. 8, pp. 2222–2232 Jan-2020
  4. Yong Chen, Pui In Mak, Zunsong Yang, Chirn Chye Boon, R. P. Martins, A 0.0071-mm² 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis

    IEEE Transactions on Circuits and Systems I: Regular Paper

     Vol.66, No.10, pp.3991-4004 Oct-2019
  5. Yong Chen, Zunsong Yang, Xiaoteng Zhao, Yunbo Huang, A 6.5×7 µm2 0.98-to-1.5 mW Non-Self-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4 to 44 GHz)

    IEEE Solid-State Circuits Letters

     Vol.2, Issue: 5, pp. 37-40 May-2019
  1. Zunsong Yang, Yong Chen, Shiheng Yang, Pui In Mak, R. P. Martins, A 25.4-to-29.5GHz 10.2mW Isolated-Sub-Sampling PLL (iSS-PLL) Achieving -252.9dB Jitter-power FOM and -63dBc Reference Spur

    IEEE International Solid-State Circuits Conference (ISSCC)

     pp. 270-272 Feb-2019
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