Chio-In Ieong
楊超然 Chio-In Ieong
Year of Graduation:
Mar 2016
Ph.D. Dissertation:
Lower-power CMOS processors design for ECG QRS wave detection and data compression
Current Appointment:
Design Engineer at Hisilicon (Huawai), Shenzhen, China
Awards
Total:1
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ISSCC Student Travel Grant Award
IEEE Solid-State Circuits Society (2016)
Feb-2016
Patents and Technology Transfer
Total:0
Journals and magazines
Total:4
Conference papers and presentations
Total:8
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“Student Research Preview,”
IEEE International Solid-State Circuits Conference (ISSCC)
Session 2, Paper No. 3 Feb-2016 -
Sub-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform and Maxima Modulus Pair Recognition for Power-Efficient Wireless Arrhythmia Monitoring
Asia and South Pacific Design Automation Conference (ASP-DAC)
Jan-2016
Books and Book Chapters
Total:0