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He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Silk-Road Award (A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS)

Digest of Technical Papers from IEEE International Solid-State Circuits Conference – ISSCC 2011

 [Awarded for best asian PhD student research in ISSCC (“World Chip Olympic”)] Feb-2011
Pui In Mak, Academic Staff Award

University of Macau

 Jan-2011
Chio-In Ieong, Mang I Vai, Peng Un Mak, Pui In Mak, ECG Heart Beat Detection Via Mathematical Morphology and Quadratic Spline Wavelet Transform

IEEE International Conference on Consumer Electronics (ICCE)

 pp 609- 610 Jan-2011
Guohe Yin, U-Fat Chio, He Gong Wei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Zhihua Wang, An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications

IEEE International Conference on Electronics, Circuits and Systems (ICECS)

 pp. 878-881 Dec-2010
Seng-Pan U, Honorary Title of Value of 2010 ( An annual government decoration for Macau citizen who has great contribution to Macau SAR reputation, development and society advancement)

Macau SAR Government

 Dec-2010
Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators

IEEE International Conference on Electronics, Circuits and Systems (ICECS

 pp. 547-550 Dec-2010
Pui In Mak, R. P. Martins, High-/Mixed-Voltage RF and Analog CMOS Circuits Come of Age

IEEE CAS Magazine

 vol. 10, Issue 4, pp. 27-39 Dec-2010
JIANG Yang, Kim Fai Wong, Chenyan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators

in IEEE International Conference on Electronics, Circuits and Systems (ICECS)

 pp.547-550 Dec-2010
Li Ding, Sai Weng Sin, Seng-Pan U, R. P. Martins, An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs

IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

 pp. 208-211 Dec-2010
Yang Jiang, Kim Fai Wong, ChenYan Cai, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators

IEEE Asia Pacific Conference on Circuit and Systems (APCCAS)

 pp. 1011-1014 Dec-2010
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