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Conference papers and presentations

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Category: Conference papers and presentations Total: 532
Yun Du, Tao He, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A robust NTF Zero Optimization Technique for both Low and High OSRs Sigma-Delta Modulators

in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

 Dec-2012
WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

 pp 268-271 Dec-2012
Tao He, Yun Du, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A DT 0–2 MASH ΣΔ Modulator with VCO-Based Quantizer for Enhanced Linearity

in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

 Dec-2012
Zhicheng Lin, Pui In Mak, R. P. Martins, A 1.7mW 0.22mm2 2.4GHz ZigBee RX Exploiting a Current-Reuse Blixer + Hybrid Filter Topology in 65nm CMOS

International Solid-State Circuits Conference, ISSCC 2013

 pp 448-449 Dec-2012
Yanjie Xiao, Tan-Tan Zhang, Pui In Mak, Man-Kay Law, R. P. Martins, A 0.8-μW 8-Bit 1.5~20-pF-Input-Range Capacitance-to-Digital Converter for Lab-on-Chip Digital Microfluidics Systems

IEEE Biomedical Circuits and Systems Conference (BIOCAS)

 pp 384-387 Nov-2012
Zhijie Chen, Yang Jiang, ChenYan Cai, He Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application

IEEE Asian Solid-State Circuit Conference – (A-SSCC)

 pp 257-260 Nov-2012
Jianyu Zhong, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Inter-Stage Gain Error Self-Calibration of a 31.5fJ 10b 470MS/s Pipelined-SAR ADC

IEEE Asian Solid-State Circuit Conference – (A-SSCC)

 pp 153-156 Nov-2012
Zhijie Chen, JIANG Yang, Chenyan Cai, He-Gong Wei, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 22.4μW 80dB SNDR ΣΔ Modulator with Passive Analog Adder and SAR Quantizer for EMG Application

in IEEE Asian Solid State Circuits Conference (A-SSCC)

 Nov-2012
Guohe Yin, He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS

IEEE European Solid-State Circuits Conference – ESSCIRC 2012

 pp 377-380 Sep-2012
Rui Wang, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique

IEEE European Solid-State Circuits Conference – ESSCIRC 2012

 pp 265-268 Sep-2012
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