Research Group

Yong Chen, Pui In Mak, Stefano D'Amico, Li Zhang, He Qian, Yan Wang, A Single-Branch Third-Order Pole–Zero Low-Pass Filter With 0.014-mm2 Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth–Power Scalability

IEEE Transactions on Circuits and Systems – II

Vol. 60, No. 11, pp. 761-765 Nov-2013

Yaohua Zhao, Pui In Mak, Man-Kay Law, R. P. Martins, A 0.127-mm2, 5.6-mW, 5th-Order SC LPF with +23.5-dBm IIP3 and 1.5-to-15-MHz Clock-Defined Bandwidth in 65-nm CMOS

IEEE Asian Solid-State Circuits Conference (A-SSCC)

pp 361-364 Nov-2013

He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Silk-Road Award (A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS)

Digest of Technical Papers from IEEE International Solid-State Circuits Conference – ISSCC 2011

[Awarded for best asian PhD student research in ISSCC (“World Chip Olympic”)] Feb-2011

Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, IEEE A-SSCC Student Design Contest Best Design Award (A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation)

IEEE Asian Solid-State Circuits Conference

Nov-2011

WenLan Wu, Monotonic Multi-Switching Method for Ultra-Low-Voltage Energy Efficient SAR ADCs Jun-2013

Chi Hang Chan, Scientific and Technological R&D Award (Master Student)

The Science and Technology Development Fund

Oct-2012

Li Ding, Seng-Pan U, 500M High Speed ADC

UMC

90n High Speed SAR ADC Oct-2013

ChenYan Cai, Low Power High Efficiency Excess-Loop-Delay Compensation Techniques in Continuous-Time Delta-Sigma Modulators University of Macau, AMSV May-2013

Li Ding, Seng-Pan U, 0.46mm2 4-db NF unified Receiver Front end chip

ST

65nm A 12-bit 160-Ms/s Passive Pipeline-SAR ADC Oct-2013

Seng-Pan U, R. P. Martins, J.E.Franca, Switched-Capacitor Interpolators Without the Input Sample-and-Hold Filtering Effect

IEE Electronics Letters

Vol. 32, Issue 10, pp 879-881 May-1996