A A A

Data Conversion and Signal Processing

Home/Research Group/Data Conversion and Signal Processing
Category: Data Conversion and Signal Processing Total: 481
Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS

in Journal of Semiconductor Technology and Science

 vol. 16, issue 4, pp. 395-404 Aug-2016
Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Seng-Pan U, R. P. Martins, A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration

IEEE International Solid-State Circuits Conference (ISSCC)

 pp. 282-284 Feb-2017
Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Chon-Lam Lio, Seng-Pan U, R. P. Martins, A 0.011mm2 60dB SNDR 100MS/s Reference Error Calibrated SAR ADC with 3pF Decoupling Capacitance for Reference Voltages

IEEE Asian Solid-State Circuits Conference (A-SSCC)

 pp. 145-148 (highlighted paper and invited to JSSC special issue) Nov-2016
Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching

IEEE ISCAS 2017

 accepted Oct-2016
Jiang DongYang, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Reconfigurable mismatch-free time-interleaved bandpass sigma–delta modulator for wireless communications

Electronics Letters

 Vol. 53 , Issue: 7, pp 506 - 508 Mar-2017
Dezhi Xing, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Fan Ye, Junyan Ren, Seng-Pan U, R. P. Martins, Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

 Vol.25, Issue 3, pp.1168-1172 Mar-2017
Chi Hang Chan, Yan Zhu, Sai Weng Sin, Boris Murmann, Seng-Pan U, R. P. Martins, Metastablility in SAR ADCs

press in IEEE Transactions on CAS – Part II: Express Briefs

 Volume: 64, Issue: 2, pp.111 - 115 Feb-2017
Chi Hang Chan, Yan Zhu, Ho Iok Meng, Zhang WaiHong, Seng-Pan U, R. P. Martins, A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with Background Offset Calibration

IEEE International Solid-State Circuits Conference (ISSCC)

 pp. 282-284 Feb-2017
Dante Gabriel Muratore, Alper Akdikmen, Edoardo Bonizzoni, Franco Maloberti, U-Fat Chio, Sai Weng Sin, R. P. Martins, An 8-bit 0.7-GS/s Single Channel Flash-SAR ADC in 65-nm CMOS Technology

. IEEE European Solid-State Circuits Conference – ESSCIRC 2016

 pp. 421-424 Sep-2016
Jianyu Zhong, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction

IEEE European Solid-State Circuits Conference – ESSCIRC 2016

 pp. 169-172 Sep-2016
Publication
Go to Top