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Jiang DongYang

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Jiang DongYang
姜冬陽 Jiang DongYang
PhD
  1. Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance

    IEEE Journal of Solid-State Circuits

     vol. 55, No. 2, pp. 344-355 Mar-2020
  2. Jiang DongYang, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Reconfigurable mismatch-free time-interleaved bandpass sigma–delta modulator for wireless communications

    Electronics Letters

     Vol. 53 , Issue: 7, pp 506 - 508 Mar-2017
  1. Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

    2020 Symposium on VLSI Circuits Digest of Technical Papers

     Jun-2020
  2. Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ÄÓ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

    CICC 2020

     Mar-2020
  3. Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS

    IEEE International Solid-State Circuits Conference (ISSCC 2019)

     pp.336-338 Feb-2019
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