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Jiaji Mao

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Jiaji Mao
毛佳​​驥 Jiaji Mao
Master
  1. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration

    IEEE Journal of Solid-State Circuits

     vol. 55, Issue 3, pp. 693-705 (invited special issue of CICC) Mar-2020
  1. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing

    IEEE Symposium on VLSI Circuits (VLSI)

     Jun-2019
  2. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration

    IEEE Custom Integrated Circuits Conference (CICC)

     Apr-2019
  3. Jiaji Mao, Mingqiang Guo, Sai Weng Sin, R. P. Martins, A 14-bit Split Pipeline ADC with Self-Adjusted Opamp-Sharing Duty Cycle

    IEEE International Solid-State Circuits Conference – ISSCC 2018

     Ph.D. Student Research Preview - Session 3, Paper No.7 Feb-2018
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