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He Gong Wei, Chi Hang Chan, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

IEEE Journal of Solid-State Circuits

 Vol.47, no11, pp. 2763-2772 Nov-2012
Yun Du, Tao He, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

 pp 29-32 Dec-2012
Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

 pp 33-36 Dec-2012
WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

 pp 268-271 Dec-2012
Zimu Yuan, Wei Li, Adam C. Champion, Wei Zhao, An Efficient Hybrid Localization Scheme for Heterogeneous Wireless Networks

", 2012 IEEE Global Communications Conference (GLOBECOM)

 pp 372-378 Dec-2012
Zimu Yuan, Wei Li, Adam C. Champion, Wei Zhao, An Efficient Hybrid Localization Scheme for Heterogeneous Wireless Networks

", 2012 IEEE Global Communications Conference (GLOBECOM)

 pp 372-378 Dec-2012
Yun Du, Tao He, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A robust NTF Zero Optimization Technique for both Low and High OSRs Sigma-Delta Modulators

in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

 Dec-2012
Tao He, Yun Du, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

 pp 33-36 Dec-2012
Tao He, Yun Du, JIANG Yang, Sai Weng Sin, Seng-Pan U, R. P. Martins, A DT 0–2 MASH ΣΔ Modulator with VCO-Based Quantizer for Enhanced Linearity

in IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

 Dec-2012
WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array

IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

 pp 268-271 Dec-2012
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