Data Conversion and Signal Processing

A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS

2013 May 02 | Thu

...

Delay Generator

2013 May 01 | Wed

...

A 0.6V 8B 100MS/s SAR ADC with Minimized DAC Capacitance and Switching Energy in 65nm CMOS

2013 May 01 | Wed

...

A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption

2013 Apr 01 | Mon

...

N-Bits Successive Approximation Register Analog-to-Digital Converting System

2013 Jan 01 | Tue

...

A 50fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

2012 Dec 30 | Sun

...

An 8-b 400-MS/s 2-b-Per-Cycle SAR ADC With Resistive DAC

2012 Dec 03 | Mon

...

A Robust NTF Zero Optimization Technique for Both Low and High OSRs Sigma-Delta Modulators

2012 Dec 02 | Sun

...

A DT 0-2 MASH Modulator with VCO-Based Quantizer for Enhanced Linearity

2012 Dec 02 | Sun

...

A 10-bit SAR ADC With Two Redundant Decisions and Splitted-MSB-Cap DAC Array

2012 Dec 02 | Sun

...