Data Conversion and Signal Processing

Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ÄÓ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

CICC 2020

Mar-2020

Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration

IEEE Journal of Solid-State Circuits

vol. 55, Issue 3, pp. 693-705 (invited special issue of CICC) Mar-2020

Wenning Jiang, Yan Zhu, Chi Hang Chan, R. P. Martins, A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier

IEEE Journal of Solid-State Circuits

vol. 55, no. 2, pp. 322-332 Feb-2020

Yan Song, Chi Hang Chan, Yan Zhu, R. P. Martins, A 12.5-MHz Bandwidth 77-dB SNDR SAR-Assisted Noise Shaping Pipeline ADC

IEEE Journal of Solid-State Circuits

vol. 55, no. 2, pp. 312-321 Feb-2020

Wei Wang, Chi Hang Chan, Yan Zhu, R. P. Martins, A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization

IEEE Journal of Solid-State Circuits

vol. 55, no. 6, pp. 1588-1598 Jun-2020

Zihao Zheng, Lai Wei, Chi Hang Chan, Jan Craninckx, Jorge Lagos Benites, Pipelined analogue to digital converter

EP 20157326.8

EUROPEAN (under review)

Jul-2020

Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, Single-Loop Linear-Exponential Multi-Bit Incremental Analog-to-Digital Converter

No. 10,644,718 B1

US Patent

Jul-2020

Wei Wang, Chi Hang Chan, Yan Zhu, R. P. Martins, A 100-MHz BW 72.6-dB-SNDR CT ΔΣ Modulator Utilizing Preliminary Sampling and Quantization

IEEE Journal of Solid-State Circuits

vol. 55, no. 6, pp. 1588-1598 Jun-2020

Kai Xing, Lei Wang, Yan Zhu, Chi Hang Chan, R. P. Martins, A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SABELD-Merged Integrator and 3-Stage Opamp

2020 Symposia on VLSI Technology and Circuits

Jun-2020

Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

2020 Symposium on VLSI Circuits Digest of Technical Papers

Jun-2020