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Jianwei Lui

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Jianwei Lui
劉建偉 Jianwei Lui
PhD
  1. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS

    in Journal of Semiconductor Technology and Science

     vol. 16, issue 4, pp. 395-404 Aug-2016
  2. Jianwei Lui, Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     Issue 24, Issue 7, pp. 2603-2607 Jan-2016
  1. Jianwei Lui, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 89fJ-FOM 6-bit 3.4GS/s flash ADC with 4x time-domain interpolation

    IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015

     pp.1-4 Nov-2015
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