Research Group

Category: Research Group Total: 1207

Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, Merit Paper Award (On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC)

awarded from The 2005 Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC)

Apr-2005

Ka Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R. P. Martins, A Multistandard Transmitter D/A Interface with Embedded Frequency Up-Conversion and Two-Step Channel Selection

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 215-220 Oct-2004

Hon-Weng Chong, Kai-Yiu Che, Seng-Pan U, R. P. Martins, A 1-V 2.56-MHz Clock-Rate CMOS Multi-bit Sigma-Delta Modulator with Reset-Opamp Technique and Pseudo Data-Weighted-Averaging for Portable Audio Data Acquisition System

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 180-185 Oct-2004

Ka Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R. P. Martins, A Multistandard Transmitter D/A Interface with Embedded Frequency Up-Conversion and Two-Step Channel Selection

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 215-220 Oct-2004

Kai-Yiu Che, Hon-Weng Chong, Seng-Pan U, R. P. Martins, A 1-V 5.12-MHz Sampling-Rate 13-bit CMOS Sigma-Delta Modulator Using Reset-Opamp Technique for Portable Aduio Data Acquistion System

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 186-191 Oct-2004

Hon-Weng Chong, Kai-Yiu Che, Seng-Pan U, R. P. Martins, A 1-V 2.56-MHz Clock-Rate CMOS Multi-bit Sigma-Delta Modulator with Reset-Opamp Technique and Pseudo Data-Weighted-Averaging for Portable Audio Data Acquisition System

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 180-185 Oct-2004

Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, Model, Characterization and Solutions of Unstable Reference Voltage for Very-High-Speed Pipelined A/D Converters

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 138-143 Oct-2004

Sai Weng Sin, Seng-Pan U, R. P. Martins, Novel Low Jitter Multi-Phase Clock Generation Scheme for Parallel Analog-to-Digital Conversion Systems

Proc. IEEE/IEEJapan International Analog VLSI Workshop – AVLSIWS 2004

pp. 172-175 Oct-2004

Pui In Mak, Ka Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R. P. Martins, A Complex Low-IF Transceiver Architecture for Relaxing Phase Noise and Settling Time Requirements of RF PLL-FS

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 221-226 Oct-2004

Pui In Mak, Seng-Pan U, R. P. Martins, A Power-and-Area Efficient, Multifunctional CMOS A/D Interface for a Low-IF/Zero-IF Reconfigurable Receiver

", in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

pp. 233-238 Oct-2004

Achievements