The Distinguished Lecture on “High-Performance Low-Dropout Regulator and EDA Technologies” will take place as follows:
Date: 29 June 2023 (Thursday)
Time: 15:00 – 16:30
Venue: To be held online via Zoom (https://umac.zoom.us/j/93409740876?pwd=RENySWtMVFE5K0kwSUpPY3RWeTdtUT09)
The speaker is:
Prof. LIU Xiaosen, Associate Professor, School of Integrated Circuits, Tsinghua University
The Lecture is:
High-Performance Low-Dropout Regulator and EDA Technologies
Abstract:
With the rapid development of high-performance computing (HPC) such as CPU, GPU, 5G applications, the correspondent system-on-chip (SoC)’s power consumption increases drastically. Therefore, the conventional power management technology cannot fit for their stringent needs and becomes a critical “Power Wall” for performance evolution and bottleneck in the development of SoCs.
This talk discusses multiple power management-related researches: A TRLDO is proposed to provide regulation for PCIe 5 applications in either saturation or triode region, thus achieving low DO (60mV), high PCE (92%) despite large routing parasitics in 4nm CMOS while occupying small die area (0.137 sq-mm).
An analog layout generator based DLDO with a self-triggered binary search windowed flash ADC is proposed in 22nm CMOS to maximize the productivity of implementing analog circuit blocks in scaled CMOS process, thus significantly improving the physical design time & effort up to 60× compared with conventional manual approach.
A self-triggered binary search mechanism with a delay-based architecture is proposed to reduce the exponentially growing kickback noise and energy consumption of a traditional flash ADC down to the level of a SAR ADC while maintaining its high-speed feature. The DLDO features 3.55ps FoM and fully automatic generation.
Biography:
Prof. LIU Xiaosen is currently an Associate Professor in the School of Integrated Circuits at Tsinghua University. He received B.S. from Southeast University in 2008, M.Phil. from HKUST in 2011 and Ph.D. from Texas A&M University, College Station, in 2016. His current research interests include power management, integrated circuits, III-V semiconductor PMIC and electronic design automation.
From 2016 to 2022, he worked at the Circuit Research Lab (CRL) of Intel Labs, Oregon, USA as a staff scientist. He drove the analog & mixed-signal research, including power management architectures for emerging SoCs and advanced EDA in sub-10-nm CMOS technology. His research promoted many Intel’s product lines including Core™ and Xeon® series processor, PCH chipset, XMM™ 5G Modem, and AES hardware in x86 Arch. He has published more than 40 articles and more than 30 U.S. patents. He serves as TPC for IEEE DAC and liaison for Semiconductor Research Corporation (SRC).
For more details, kindly find the event poster, abstract and bio.
