2023-10-09T12:23:20+08:002023-10-09|News&Events, Events|

The Distinguished Lecture on “Revisit Cross-layer Co-design: Cases of Reliable and Intelligent Systems” will take place as follows:

Date: 10 October 2023 (Tuesday)

Time: 11:00 am – 12:30 pm

Venue: Research Building N21, 3/F, Room 3004

The speaker is:

Prof. GUO Xinfei, Assistant Professor, Shanghai Jiao Tong University (SJTU)


The Lecture is:

Revisit Cross-layer Co-design: Cases of Reliable and Intelligent Systems



Optimizing today computing systems requires a collaborative efforts across the whole system stack starting from transistors, through circuit and architecture up to the whole system and ecosystems. Single layer solution such as technology scaling or architectural innovation need to work together in a more effective way to ensure a lower cost. The key idea of the cross-layer co-design is to divide a metric optimal task into a set of sub tasks, which can be implemented at different levels of a system stack. Examples of such tasks can be error prediction or detection, security, power optimization, etc. These tasks can be treated as steps that the system follows to handle a particular effect even as they may not occur sequentially. In this talk, I would like to share two cases that are enabled by cross-layer co-design. 1) Designing reliable chips that are against reliability threats. On top of the power requirements, reliability becomes increasingly critical for intelligent computing such as autonomous systems, implantable devices and more. Reliability issues such as aging will not only shorten the lifetime of the chip, they will also degrade performance over time. The added margin or techniques for addressing reliability issues will further blow up the already limited power budget. As a consequence, designing a high-quality chip requires leveraging of a ton of decisions and tradeoffs. We propose a completely new research direction on fixing chip reliability issues through accelerated self-healing, in which chip aging issues follow a “circadian rhythm” behavior and can be recovered via active techniques. This approach is implemented across the system hierarchy. 2) Mixed-size quantization for edge intelligent systems. Layer-wise mixed-precision quantization (MPQ) has become prevailing for edge inference since it strikes a better balance between accuracy and efficiency compared to the uniform quantization scheme. I will discuss a cross-layer approach which integrates novel MPQ search algorithms with novel hardware design approaches. At the software level, the algorithm obtains an optimal scheme by layer-wise sensitivity with respect to a newly proposed metric that incorporates both accuracy and proxy of hardware cost. At the hardware level,  we propose to tightly integrate the quantized inference units as part of the processor pipeline through micro-architecture and Instruction Set Architecture (ISA) co-design.



Prof. GUO Xinfei is a tenure-track assistant professor at UM-SJTU Joint Institute at Shanghai Jiao Tong University (SJTU) in China, where he leads the Intelligent Circuits, Architectures and Systems (iCAS) lab. He received his Ph.D. in Computer Engineering from the University of Virginia. He also holds a Master degree in Electrical and Computer Engineering from the University of Florida. Before joining academia, he worked at Nvidia and IBM research in the United States, where he served as a key member to contribute to multiple chip products, including the world-leading BlueField Data Processing Units (DPU) and a total of 7 chip tapeouts that cover a wide range of technology nodes from 180nm to 7nm. His previous work has resulted in over 40 conference or journal papers in design, EDA or FPGA fields. He also published a Springer book. He received best paper awards as a co-author at SOCC 2022, LASCAS 2019 and SELSE 2017. He also received multiple best presentation awards at various conferences. He was a recipient of the 2017 IEEE CASS Pre-doctoral fellowship. Currently, he serves as Associate Editor-in-Chief for IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION SYSTEMS, Associate Editor for Elsevier Integration, the VLSI Journal, and PC member or chair positions for over 30 international conferences, such as DAC, CICC, ICCAD, ASPDAC, FCCM, HOST and more. His team currently focuses on low-power and high-reliability computing, machine learning-assisted EDA techniques and reconfigurable computing architectures.


For more details, kindly find the event poster, abstract and bio.