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Conference papers and presentations

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Category: Conference papers and presentations Total: 511
Weng Ieng Mok, Pui In Mak, Seng-Pan U, R. P. Martins, On-Chip Unsteady Reference Voltage Compensation Techniques for Very-High-Speed Pipelined ADC

in Proc. of Regional Inter-University Postgraduate Electrical and Electronic Engineering Conference (RIUPEEEC)

 pp. 276-280 Jun-2005
Sai Weng Sin, Seng-Pan U, R. P. Martins, A Novel Low-Voltage Cross-Coupled Passive Sampling Branch for Reset- and Switched-Opamp Circuits

in Proc.of IEEE International Symposium on Circuits and Systems (ISCAS)

 vol. 2, pp. 1585-1588 May-2005
Chon-In Lao, Seng-Pan U, R. P. Martins, A Novel Semi-MASH Sub-stage for High-order Cascade Sigma-Delta Modulators

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 vol. 4, pp. 3095-3098 May-2005
Sai Weng Sin, Seng-Pan U, R. P. Martins, A Novel Very Low-Voltage SC-CMFB Technique for Fully-Differential Reset-Opamp Circuits

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 vol. 2, pp. 1581-1584 May-2005
Kin-Sang Chio, Seng-Pan U, R. P. Martins, A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 pp. 3099-3102 May-2005
Ka Hou Ao Ieong, Chong-Yin Fok, Pui In Mak, Seng-Pan U, R. P. Martins, A Frequency Up-Conversion and Two-Step Channel Selection Embedded CMOS D/A Interface

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 vol. 1, pp. 392-395 May-2005
Sai Weng Sin, Seng-Pan U, R. P. Martins, Novel Low Jitter Multi-Phase Clock Generation Scheme for Parallel Analog-to-Digital Conversion Systems

Proc. IEEE/IEEJapan International Analog VLSI Workshop – AVLSIWS 2004

 pp. 172-175 Oct-2004
Pui In Mak, Seng-Pan U, R. P. Martins, A Power-and-Area Efficient, Multifunctional CMOS A/D Interface for a Low-IF/Zero-IF Reconfigurable Receiver

", in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

 pp. 233-238 Oct-2004
Ka Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R. P. Martins, A Multistandard Transmitter D/A Interface with Embedded Frequency Up-Conversion and Two-Step Channel Selection

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

 pp. 215-220 Oct-2004
Pui In Mak, Ka Hou Ao Ieong, Chong-Yin Fok, Seng-Pan U, R. P. Martins, A Complex Low-IF Transceiver Architecture for Relaxing Phase Noise and Settling Time Requirements of RF PLL-FS

in Proc. of IEEJ (7th) International Analog VLSI Workshop (AVLSIWS)

 pp. 221-226 Oct-2004
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