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Data Conversion and Signal Processing

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Category: Data Conversion and Signal Processing Total: 483
Sai Weng Sin, Seng-Pan U, R. P. Martins, Novel Timing-Skew-Insensitive, Multi-phase Clock Generation Scheme for Parallel DAC and N-Path Filter

Proc. IEEE/IEE Regional Inter-University Post-graduate EEE Conference – RIUPEEEC 2006

 pp. 133-136 Jul-2006
Jun-Xia Ma, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 1.8V 1.056GS/s 6-b Flash-Interpolation ADC for MB-OFDM UWB Applications

Proceedings of RIUPEEEC (Macao, China)

 pp. 105-108 Jul-2006
Jun-Xia Ma, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power-Efficient 1.056 GS/s Resolution-Switchable 5-bit/6-bit Flash ADC for UWB Applications

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 pp. 4305-4308 May-2006
Sai Weng Sin, Seng-Pan U, R. P. Martins, A Novel Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits

in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS)

 pp. 3794-3797 May-2006
Chon-In Lao, Seng-Pan U, R. P. Martins, A Novel Effective Bandpass Semi-MASH Sigma-Delta Modulator with Double-Sampling Mismatch-Free Resonator

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 pp. 581-584 May-2006
Kin-Sang Chio, Seng-Pan U, R. P. Martins, A Dual-Mode Low-Distortion Sigma-Delta Modulator with Relaxing Quantization Level

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 pp. 1892-1895 May-2006
Sai Weng Sin, Seng-Pan U, R. P. Martins, A Novel Low-Voltage Finite-Gain Compensation Technique for High-Speed Reset- and Switched-Opamp Circuits

in Proc. of 2004 IEEE International Symposium on Circuits and Systems (ISCAS)

 pp. 3794-3797 May-2006
Chon-In Lao, Seng-Pan U, R. P. Martins, A Novel Effective Bandpass Semi-MASH Sigma-Delta Modulator with Double-Sampling Mismatch-Free Resonator

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 pp. 581-584 May-2006
Kin-Sang Chio, Seng-Pan U, R. P. Martins, A Dual-Mode Low-Distortion Sigma-Delta Modulator with Relaxing Quantization Level

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 pp. 1892-1895 May-2006
Jun-Xia Ma, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Power-Efficient 1.056 GS/s Resolution-Switchable 5-bit/6-bit Flash ADC for UWB Applications

in Proc. of IEEE International Symposium on Circuits and Systems (ISCAS)

 pp. 4305-4308 May-2006
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