Data Conversion and Signal Processing

A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure

2012 Jun 02 | Sat

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A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC

2012 Jun 01 | Fri

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A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure

2012 Jun 01 | Fri

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Travel Grant Award (A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure)

2012 Jun 01 | Fri

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2012 Best Master Thesis Award in Tsinghua University

2012 Jun 01 | Fri

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A 10MHz BW 78dB DR CT ΣΔ Modulator with Novel Switched High Linearity VCO-Based Quantizer

2012 May 02 | Wed

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Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs

2011 Nov 30 | Wed

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Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation

2011 Nov 30 | Wed

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A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

2011 Nov 28 | Mon

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A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

2011 Nov 26 | Sat

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