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Data Conversion and Signal Processing

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Category: Data Conversion and Signal Processing Total: 481
He Gong Wei, Scientific and Technological R&D Award (PhD Student), Macau Science and Technology Award 2012

FDCT

 Oct-2012
Chi Hang Chan, Scientific and Technological R&D Award (Master Student)

The Science and Technology Development Fund

 Oct-2012
Guohe Yin, He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS

IEEE European Solid-State Circuits Conference – ESSCIRC 2012

 pp 377-380 Sep-2012
Rui Wang, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique

IEEE European Solid-State Circuits Conference – ESSCIRC 2012

 pp 265-268 Sep-2012
Guohe Yin, He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 0.024mm2 4.9 fJ 10-Bit 2MS/s SAR ADC in 65 nm CMOS

IEEE European Solid-State Circuits Conference – ESSCIRC 2012

 pp 377-380 Sep-2012
Rui Wang, U-Fat Chio, Sai Weng Sin, Seng-Pan U, Zhihua Wang, R. P. Martins, A 12-Bit 110MS/S 4-Stage Single-Opamp Pipelined SAR ADC with Ratio-Based GEC Technique

IEEE European Solid-State Circuits Conference – ESSCIRC 2012

 pp 265-268 Sep-2012
ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators

IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2012

 pp 1096-1099 Aug-2012
Si-Seng Wong, U-Fat Chio, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted Time-Interleaved SAR ADC

IEEE Custom Integrated Circuits Conference – CICC 2012

 pp 1-4 Aug-2012
ChenYan Cai, Yang Jiang, Sai Weng Sin, Seng-Pan U, R. P. Martins, An ELD Tracking Compensation Technique for Active-RC CT ΣΔ Modulators

IEEE Int. Midwest Symposium on Circuits and Systems (MWSCAS) 2012

 pp 1096-1099 Aug-2012
Yan Zhu, Chi Hang Chan, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC

2012 Symposium on VLSI Circuits Digest of Technical Papers

 pp 90-91 Jun-2012
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