Data Conversion and Signal Processing

Chi Hang Chan, Yan Zhu, Yan Lu, Sai Weng Sin, R. P. Martins, 2020 Macao Science & Technology Award – Technological Invention – 2nd Prize (Leading-Edge-Efficiency Data and Power Conversion Integrated Circuit Designs for Emerging Systems)

The Science and Technology Development Fund(FDCT)

Oct-2020

Yan Song, Yan Zhu, Chi Hang Chan, R. P. Martins, 9.6 A 2.56mW 40MHz-Bandwidth 75dB-SNDR Partial-Interleaving SAR-Assisted NS Pipeline ADC With Background Inter-Stage Offset Calibration

2020 IEEE International Solid- State Circuits Conference - (ISSCC)

pp. 164-166 Feb-2020

Minglei Zhang, Yan Zhu, Chi Hang Chan, R. P. Martins, 16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input

2020 IEEE International Solid- State Circuits Conference - (ISSCC)

pp. 252-254. Feb-2020

Kai Xing, Lei Wang, Yan Zhu, Chi Hang Chan, R. P. Martins, A 10.4mW 50MHz-BW 80dB-DR Single-Opamp Third-Order CTSDM with SABELD-Merged Integrator and 3-Stage Opamp

2020 Symposia on VLSI Technology and Circuits

Jun-2020

Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

2020 Symposium on VLSI Circuits Digest of Technical Papers

Jun-2020

Zihao Zheng, Lai Wei, Chi Hang Chan, Jan Craninckx, Jorge Lagos Benites, Pipelined analogue to digital converter

EP 20157326.8

EUROPEAN (under review)

Jul-2020

Biao Wang, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, Single-Loop Linear-Exponential Multi-Bit Incremental Analog-to-Digital Converter

No. 10,644,718 B1

US Patent

Jul-2020

Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance

IEEE Journal of Solid-State Circuits

vol. 55, No. 2, pp. 344-355 Mar-2020

Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ÄÓ Modulator with Digital Feedforward Extrapolation in 28nm CMOS

CICC 2020

Mar-2020

Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration

IEEE Journal of Solid-State Circuits

vol. 55, Issue 3, pp. 693-705 (invited special issue of CICC) Mar-2020