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A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS

Home/A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS
2020-04-21T00:00:00+08:002020-04-21|Uncategorized|
2021-08-25T10:12:37+08:002019-12-01|Achievements, Research Group, Wireless IC, Type, Journals and magazines|
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