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A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS

Home/A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS
2019-12-17T00:00:00+08:002019-12-17|Uncategorized|
2019-11-01T00:00:00+08:002019-11-01|Achievements, Research Group, Wireless IC, Type, Conference papers and presentations|
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