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2 Papers Cited in ISSCC 2015 Plenary Talk

Home/2 Papers Cited in ISSCC 2015 Plenary Talk
2019-06-02T19:17:01+08:002015-02-26|Uncategorized|

IEEE International Solid-State Circuits Conference 2015 (ISSCC 2015) is held between February 22 and 26, in San Francisco, USA. The conference theme for 2015 is SILICON SYSTEMS — SMALL CHIPS for BIG DATA.

Plenary Talk Speaker Prof. Willy Sansen, Professor Emeritus, Katholieke Universiteit Leuven, Leuven, Belgium, presented “Analog CMOS from 5 Micrometer to 5 Nanometer“ and cited 2 papers from State Key Laboratory of Analog and Mixed-Signal VLSI in ISSCC 2015.

 

http://www.esat.kuleuven.be/micas/index.php/people-mainmenu-26/13-staff/12-willy-sansen

 

[15] A 0.0013mm2 3.6μW Nested-Current-Mirror Single-Stage Amplifierdriving 0.15-to-15nF Capacitive Loads with >62° Phase Margin

 

[17] A 0.016mm2 144µW Three-Stage Amplifier Capable of Driving 1-to-15nF Capacitive Load with >0.95MHz GBW

 

 WSansen-plenary-from ISSCC2015-Digest_Highlights.pdf 

 

In this year, AMSV got 4 papers and 2 Student Research Previews accepted in ISSCC 2015. PhD students Chi-Hang Chan and Zhicheng Lin presented their papers, entitled “A 5.5mW 6b 5GS/s 4-times Interleaved 3b/cycle SAR ADC in 65nm CMOS” and “A 0.028mm2 11mW Single-Mixing Blocker-Tolerant Receiver with Double-RF N-Path Filtering,  S11 Centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF”. Both PhD Students will receive the Pre-Doctoral Achievement Award in the conference too. Our Faculty Staff, Dr. Yan Lu, presented two papers, ” A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors” and ”A 2-/3-Phase Fully-Integrated Switched-Capacitor DC-DC Converter in Bulk-CMOS for Energy-Efficient Digital Circuits With 14% Efficiency Improvement” in ISSCC 2015.

Two posters are presented at the Student Research Preview also. The presented works are from the research works of PhD Students Ka-Meng Lei, ”A Multi-Step Multi-Sample µNMR Relaxometer Using Inside-Magnet Digital Microfluidics and a Butterfly-Coil-Input CMOS Transceiver”, and Jianyu Zhong, ”A 12b 180MS/S 0.068mm2 Full-Calibration-Integrated Pipelined-SAR ADC”.

 

2019-06-02T19:30:48+08:002015-02-26|News, News|

IEEE International Solid-State Circuits Conference 2015 (ISSCC 2015) is held between February 22 and 26, in San Francisco, USA. The conference theme for 2015 is SILICON SYSTEMS — SMALL CHIPS for BIG DATA.

Plenary Talk Speaker Prof. Willy Sansen, Professor Emeritus, Katholieke Universiteit Leuven, Leuven, Belgium, presented “Analog CMOS from 5 Micrometer to 5 Nanometer“ and cited 2 papers from State Key Laboratory of Analog and Mixed-Signal VLSI in ISSCC 2015.

 

http://www.esat.kuleuven.be/micas/index.php/people-mainmenu-26/13-staff/12-willy-sansen

 

[15] A 0.0013mm2 3.6μW Nested-Current-Mirror Single-Stage Amplifierdriving 0.15-to-15nF Capacitive Loads with >62° Phase Margin

 

[17] A 0.016mm2 144µW Three-Stage Amplifier Capable of Driving 1-to-15nF Capacitive Load with >0.95MHz GBW

 

 WSansen-plenary-from ISSCC2015-Digest_Highlights.pdf 

 

In this year, AMSV got 4 papers and 2 Student Research Previews accepted in ISSCC 2015. PhD students Chi-Hang Chan and Zhicheng Lin presented their papers, entitled “A 5.5mW 6b 5GS/s 4-times Interleaved 3b/cycle SAR ADC in 65nm CMOS” and “A 0.028mm2 11mW Single-Mixing Blocker-Tolerant Receiver with Double-RF N-Path Filtering,  S11 Centering, +13dBm OB-IIP3 and 1.5-to-2.9dB NF”. Both PhD Students will receive the Pre-Doctoral Achievement Award in the conference too. Our Faculty Staff, Dr. Yan Lu, presented two papers, ” A 123-Phase DC-DC Converter-Ring with Fast-DVS for Microprocessors” and ”A 2-/3-Phase Fully-Integrated Switched-Capacitor DC-DC Converter in Bulk-CMOS for Energy-Efficient Digital Circuits With 14% Efficiency Improvement” in ISSCC 2015.

Two posters are presented at the Student Research Preview also. The presented works are from the research works of PhD Students Ka-Meng Lei, ”A Multi-Step Multi-Sample µNMR Relaxometer Using Inside-Magnet Digital Microfluidics and a Butterfly-Coil-Input CMOS Transceiver”, and Jianyu Zhong, ”A 12b 180MS/S 0.068mm2 Full-Calibration-Integrated Pipelined-SAR ADC”.

 

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