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Xi Meng

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Xi Meng
孟茜 Xi Meng
  1. Peng Chen, Xi Meng, Jun Yin, Pui-In Mak, Rui P. Martins, R. B. Staszewski, A 529 μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS

    IEEE Transactions on Circuits and Systems I

     vol. 69, pp. 51–63 Jan-2022
  1. Haoran Li, Tailong Xu, Xi Meng, Jun Yin, Rui P. Martins and Pui-In Mak, A 23.2-to-26GHz Sub-Sampling PLL Achieving 48.3fsrms Jitter, -253.5dB FoMJ, and 0.55μs Locking Time Based on a Function-Reused VCO-Buffer and a Type-I FLL with Rapid Phase Alignment

    IEEE International Solid-State Circuits Conference (ISSCC)

     Feb-2024
  2. Xi Meng, Junqi Guo, Haoran Li, Jun Yin, Pui-In Mak, Rui P. Martins, A 15.2-to-18.2GHz Balanced Dual-Core Inverse-Class-F VCO with Q-Enhanced 2nd-Harmonic Resonance Achieving 187-to-188.1dBc/Hz FoM in 28nm CMOS

    2021 IEEE Asian Solid-State Circuits Conference (A-SSCC)

    Session 12/ Paper 12.1

     Nov-2021
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