The Distinguished Lecture on “Design of Low Jitter Compact PLLs” will take place as follows:
Date: 30 July 2025 (Wednesday)
Time: 11:00 am – 12:00 pm
Venue: Research Building N21, G013
The speaker is:
Prof. WANG Hui, Associate Professor, Shanghai Jiao Tong University, China
The Lecture is:
Design of Low Jitter Compact PLLs
Abstract:
High performance phase-locked loops (PLLs) are widely used in digital microprocessors, wireline/optical links, and data converters, among many other applications. In the meantime, an increasing number of PLLs are demanded and integrated on a single System-on-Chip for such applications. Therefore, it becomes imperative to design area efficient PLLs while without sacrificing their phase noise (PN) or jitter performance. Ring oscillator (RO)-based PLLs are extremely compact and can generate multiple output phases with wide frequency tuning range. However, the intrinsic high RO PN renders the implementation of RO-based PLLs with a low power consumption and a low PN extremely challenging. In this talk, we will go through popular techniques to suppress RO PN for compact PLL design, along with a few newly proposed methods that achieve state-of-the-art jitter performance with a small area consumption.
Biography:
Prof. WANG Hui (S’15–M’18-SM’22) received the B.Sc. degree in microelectronics from Shanghai Jiao Tong University, Shanghai, China, and the Ph.D. degree in electrical and computer engineering from the University of California at San Diego (UCSD), La Jolla, CA, USA, respectively. He is currently an Associate Professor with Shanghai Jiao Tong University (SJTU), Shanghai, China. His research focuses on high performance wireless and wireline integrated circuits design, including high-speed energy-efficient RF transceivers, frequency synthesizers, and high-speed IOs. Prior to joining Shanghai Jiao Tong University, Prof. WANG was a postdoctoral scholar with Stanford University, Stanford, CA, USA, where he researched fully integrated high throughput wireless transceivers, and worked at Qualcomm Technologies Inc. (QCT), Santa Clara, CA, USA, developing high-performance clock generation circuits.
For more details, kindly find the event poster, abstract and bio.
