A A A

Type

Home/Type
Category: Type Total: 1217
Wei-Han Yu, Xingqiang Peng, Pui In Mak, R. P. Martins, ISSCC Student Travel Grant Award
 

IEEE Solid-State Circuits Society (2016)

 Feb-2016
Ka-Meng Lei, Pui In Mak, Man-Kay Law, R. P. Martins, A-SSCC Distinguished Design Award
 

IEEE Asian Solid-State Circuits Conference (A-SSCC) (2015)

 Feb-2016
Pui In Mak, Fujian Lin, R. P. Martins, RF-to-BB-Current-Reuse Wideband Receiver with a Single-MOS Pole-Zero LPF

Granted Number: 9,270,314

US Patent

 Feb-2016
Ka-Meng Lei, Hadi Heidari, Pui In Mak, Man-Kay Law, Franco Maloberti, R. P. Martins, A Handheld 50pM-Sensitivity Micro-NMR CMOS Platform with B-Field Stabilization for Multi-Type Biological/Chemical Assays

IEEE International Solid-State Circuits Conference (ISSCC), Digest

 pp. 474-475 Feb-2016
Jun Yin, Pui In Mak, Franco Maloberti, R. P. Martins, A 0.003mm2 1.7-to-3.5GHz Dual-Mode Time-Interleaved Ring-VCO Achieving 90-to-150kHz 1/f3 Phase Noise Corner

IEEE International Solid-State Circuits Conference (ISSCC), Digest

 pp. 48-49 Feb-2016
Denis Guangyin Chen, Man-Kay Law, Yong Lian, A. Bermak, Low-power CMOS Laser Doppler Imaging using Non-CDS Pixel Readout and 13.6-bit SAR ADC

IEEE Trans. on Biomedical Circuits and Systems

 vol. 10, Issue. 1, pp. 186-199 Feb-2016
Tianlan Chen, Yanwei Jia, Cheng Dong, Jie Gao, Pui In Mak, R. P. Martins, Sub-7-second genotyping of single-nucleotide polymorphism by high-resolution melting curve analysis on a thermal digital microfluidic device

Lab on a Chip

 16, 743-752 Jan-2016
Chio-In Ieong, Pui In Mak, Mang I Vai, R. P. Martins, Sub-µW QRS Detection Processor Using Quadratic Spline Wavelet Transform and Maxima Modulus Pair Recognition for Power-Efficient Wireless Arrhythmia Monitoring

Asia and South Pacific Design Automation Conference (ASP-DAC)

 Jan-2016
Chak Fong Cheang, Ka-Fai Un, Pui In Mak, R. P. Martins, Time-Domain I/Q-LOFT Compensator Using a Simple Envelope Detector for a Sub-GHz IEEE 802.11af WLAN Transmitte

Asia and South Pacific Design Automation Conference (ASP-DAC)

 Jan-2016
Mingzhong Li, Chio-In Ieong, Man-Kay Law, Pui In Mak, Mang I Vai, Sio Hang Pun, R. P. Martins, Sub-threshold VLSI Logic Family Exploiting Unbalanced Pull-up/down Network, Logical Effort and Inverse-Narrow-Width Techniques

Asia and South Pacific Design Automation Conference (ASP-DAC)

 Jan-2016
Achievements
Go to Top