A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom 2010 Jan 01 | Fri ...
Certificate of Merit (DC-Offset-Compensated, CT/DT Hybrid Filter with Process-Insensitive Cutoff and Low In-Band Group-Delay Variation for WLAN Receivers) 2009 Dec 01 | Tue ...
EEG Signals Classification for Brain Computer Interfaces Based on Gaussian Process Classifier 2009 Dec 01 | Tue ...
A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator 2009 Nov 28 | Sat ...
Third Prize for the Final Year Project Supervised (A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator For 3G WCDMA Receivers) 2009 Nov 10 | Tue ...
A Voltage-Controlled Capacitance Offset Calibration Technique for High Resolution Dynamic Comparator 2009 Nov 01 | Sun ...