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He Gong Wei, U-Fat Chio, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation

IEEE Asian Solid-State Circuits Conference – ASSCC 2010

 pp. 1-4 Nov-2010
Chi Man Wong, Boyu Wang, Feng Wan, Peng Un Mak, Pui In Mak, Mang I Vai, An Improved Phase-Tagged Stimuli Generation Method in Steady-State Visual Evoked Potential Based Brain-Computer Interface

International Conference on Biomedical Engineering and Informatics (BMEI)

 pp. 745-749 Oct-2010
R. P. Martins, Corresponding Member of the Portuguese Academy of Sciences

Portuguese Academy of Sciences

 Oct-2010
Sai Weng Sin, Seng-Pan U, R. P. Martins, Generalized Low-Voltage Circuit Techniques for Very High-Speed Time-Interleaved Analog-to-Digital Converters

Analog Circuits and Signal Processing, Springer

 978-90-481-9709-5 Oct-2010
Boyu Wang, Chi Man Wong, Feng Wan, Peng Un Mak, Pui In Mak, Mang I Vai, Gaussian Mixture Model Based on Genetic Algorithm for Brain-Computer Interfaces

International Conference on Biomedical Engineering and Informatics (BMEI)

 pp. 4079-4083 Oct-2010
Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H

in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010

 pp. 218-221 Sep-2010
Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, A Digital Background Nonlinearity Calibration Algorithm for Pipelined ADCs

IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia)

 pp. 115-118 Sep-2010
Seng-Pan U, R. P. Martins, HLHL Scientific and Technological Innovation Award (First from Macau)

He Leung Ho Lee Foundation

 Sep-2010
Pui In Mak, Biopotential-Readout Analog Circuits – Recent Advances and Remaining Challenges

Regional Biomedical Engineering Society Conference

 pp.53 Sep-2010
Sai Weng Sin, Li Ding, Yan Zhu, He Gong Wei, Chi Hang Chan, U-Fat Chio, Seng-Pan U, R. P. Martins, An 11b 60MS/S 2.1mW Two-Step Time-Interleaved SAR-ADC with Reused S&H

in Proc. IEEE European Solid-State Circuits Conference – ESSCIRC 2010

 pp. 218-221 Sep-2010
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