Research Group

An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications

2010 Dec 31 | Fri

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A Reduced Jitter-Sensitivity Clock Generation Technique for Continuous-Time ΣΔ Modulators

2010 Dec 28 | Tue

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An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs

2010 Dec 28 | Tue

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Honorary Title of Value of 2010 ( An annual government decoration for Macau citizen who has great contribution to Macau SAR reputation, development and society advancement)

2010 Dec 09 | Thu

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An Efficient DAC and Interstage Gain Error Calibration Technique For Multi-Bit Pipelined ADCs

2010 Dec 01 | Wed

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Honorary Title of Value of 2010 ( An annual government decoration for Macau citizen who has great contribution to Macau SAR reputation, development and society advancement)

2010 Dec 01 | Wed

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An Ultra Low Power 9-bit 1-MS/s Pipelined SAR ADC for Bio-medical Applications

2010 Dec 01 | Wed

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A Fixed-Pulse Shape Feedback Technique with Reduced Clock-Jitter Sensitivity in Continuous-Time Sigma-Delta Modulators

2010 Dec 01 | Wed

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High-/Mixed-Voltage RF and Analog CMOS Circuits Come of Age

2010 Dec 01 | Wed

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A Process-insensitive Current-Controlled Delay Generator with Threshold Voltage Compensation

2010 Nov 08 | Mon

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