Research Group

A Generalized Timing-Skew-Free, Multi-Phase Clock Generation Platform for Parallel Sampled-Data Systems

2004 May 27 | Thu

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An I/Q-Multiplexed and OTA-Shared CMOS Pipelined ADC with an A-DQS S/H Front-End for Two-Step-Channel-Select Low-IF Receiver

2004 May 01 | Sat

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A Generalized Timing-Skew-Free, Multi-Phase Clock Generation Platform for Parallel Sampled-Data Systems

2004 May 01 | Sat

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A Low-IF/Zero-IF Reconfigurable Receiver with Two-Step Channel Selection Technique for Multistandard Applications

2004 May 01 | Sat

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Outstanding Mentor Award

2004 Jan 01 | Thu

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A Front-to-Back-End Modeling of I/Q Mismatch Effects in a Complex-IF Receiver for Image-Rejection Enhancement

2003 Dec 01 | Mon

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Frequency-Downconversion and IF Channel Selection A-DQS Sample-and-Hold Pair for Two-Step-Channel-Select Low-IF Receiver

2003 Dec 01 | Mon

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Bandpass Sigma-Delta Modulator SIMULINK® Non-Idealities Model with Behavior Simulation

2003 Oct 31 | Fri

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A Programmable Switched-Capacitor A-DQS Frequency Downconverter for Two-Step Channel Selection Wireless Receiver

2003 Oct 01 | Wed

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Outstanding Student Paper Award (A Programmable Switched-Capacitor A-DQS Frequency Downconverter for Two-Step Channel Selection Wireless Receiver)

2003 Oct 01 | Wed

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