Data Conversion and Signal Processing

Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area

2019 Aug 01 | Thu

...

A 5.35-mW 10-MHz Single-Opamp Third-Order CTΔΣModulator With CTC Amplifier and Adaptive Latch DAC Driver in 65-nm CMOS

2019 Aug 01 | Thu

...

Split-based time-interleaved ADC with digital background timing-skew calibration

2019 Jul 31 | Wed

...

A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH ΔΣ Modulator With Multirate Opamp Sharing

2019 Jul 30 | Tue

...

Reconfigurable mismatch-free time-interleaved bandpass sigma–delta modulator for wireless communications

2019 Jul 30 | Tue

...

A 5-bit 2 GS/s binary-search ADC with charge-steering comparators

2019 Jul 30 | Tue

...

A 550-μW 20-kHz BW 100.8-dB SNDR Linear-Exponential Multi-Bit Incremental Σ Δ ADC With 256 Clock Cycles in 65-nm CMOS

2019 Apr 01 | Mon

...

A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS

2019 Feb 01 | Fri

...

A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier

2019 Feb 01 | Fri

...

A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques

2019 Feb 01 | Fri

...