Data Conversion and Signal Processing

Clock-Jitter Sensitivity Reduction in CT Sigma-Delta Modulators Using Voltage-Crossing Detection DAC

2011 Aug 08 | Mon

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Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error

2011 Aug 08 | Mon

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Noise Shaping Implementation in Two-Step/SAR ADC Architectures Based on Delayed Quantization Error

2011 Aug 01 | Mon

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Multi-Merged-Switched Redundant Capacitive DACs for 2b/cycle SAR ADC

2011 Aug 01 | Mon

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A Dual-VCO-Based Quantizer with Highly Improved Linearity and Enlarged Dynamic Range

2011 Aug 01 | Mon

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A Charge Pump Based Timing-Skew Calibration for Time-Interleaved ADC

2011 Aug 01 | Mon

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Creativity Prize for the Final Year Project (A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator with VCO-Based Quantizer for WiMAX Application)

2011 Jun 01 | Wed

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1st Runner-Up for the Final Year Project

2011 Jun 01 | Wed

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A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and resistive DAC in 65nm CMOS

2011 Feb 25 | Fri

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Silk-Road Award (A 0.024mm2 8-bit 400 MS/s SAR ADC with 2-bit per Cycle and Resistive DAC in 65 nm CMOS)

2011 Feb 01 | Tue

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