Data Conversion and Signal Processing

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

2011 Nov 28 | Mon

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A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

2011 Nov 26 | Sat

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A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators

2011 Nov 26 | Sat

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A 4.8-bit ENOB 5-bit 500MS/s binary-search ADC with minimized number of comparators

2011 Nov 01 | Tue

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A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

2011 Nov 01 | Tue

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IEEE A-SSCC Student Design Contest Best Design Award (A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation)

2011 Nov 01 | Tue

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Design Techniques for Nanometer Wideband Power-Efficient CMOS ADCs

2011 Nov 01 | Tue

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Hybrid Loopfilter Sigma-Delta Modulator With NTF Zero Compensation

2011 Nov 01 | Tue

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A 35 fJ 10b 160 MS/s Pipelined-SAR ADC with Decoupled Flip-Around MDAC and Self-Embedded Offset Cancellation

2011 Nov 01 | Tue

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A time-efficient dither-injection scheme for pipelined SAR ADC

2011 Oct 28 | Fri

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