Data Conversion and Signal Processing

Chi Hang Chan, Yan Zhu, Sai Weng Sin, Seng-Pan U, R. P. Martins, Franco Maloberti, Travel Grant Award (A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure)

2012 IEEE Symposium on VLSI Circuits – VLSI 2012

Jun-2012

U-Fat Chio, Scientific and Technological R&D Award (PhD Student), Macau Science and Technology Award 2012

FDCT

Oct-2012

Yan Zhu, Scientific and Technological R&D Award (PhD Student), Macau Science and Technology Award 2012

FDCT

Oct-2012

He Gong Wei, Scientific and Technological R&D Award (PhD Student), Macau Science and Technology Award 2012

FDCT

Oct-2012

Yun Du, Tao He, Creativity Prize for the Final Year Project (A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator with VCO-Based Quantizer for WiMAX Application)

2011 IEEE Project Competition

Jun-2011

Pengyu Yan, Zhiyuan Chen, 1st Runner-Up for the Final Year Project

2011 IEEE Project Competitions

Jun-2011

Yuan Fei, Sai Weng Sin, Seng-Pan U, R. P. Martins, Bronze Leaf Certificate (A nonlinearity digital background calibration algorithm for 2.5bit/stage pipelined ADCs with opamp sharing architecture)

IEEE Asia Pacific Conference on Postgraduate Research in Micro-electronics & Electronics (PrimeAsia)

Oct-2011

Yan Zhu, Chi Hang Chan, Seng-Pan U, R. P. Martins, A 10.4-ENOB 120MS/s SAR ADC with DAC Linearity Calibration in 90nm CMOS

IEEE Asian Solid-State Circuit Conference – (A-SSCC)

pp 69-72 Nov-2013

Li Ding, WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 13-bit 60M Split Pipelined ADC with Background Gain and Mismatch Error Calibration

IEEE Asian Solid-State Circuit Conference – (A-SSCC),

pp 77-80 Nov-2013

Li Ding, WenLan Wu, Sai Weng Sin, Seng-Pan U, R. P. Martins, A 13-bit 60M Split Pipelined ADC with Background Gain and Mismatch Error Calibration

IEEE Asian Solid-State Circuit Conference – (A-SSCC),

pp 77-80 Nov-2013