Data Conversion and Signal Processing

A 1.2-V 10-bit 60-360MS/s Time-Interleaved Pipelined ADC in 0.18um CMOS with Minimized Supply Headroom

2014 Mar 24 | Mon

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Analog to Digital Converter Circuit

2014 Mar 01 | Sat

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Delay Generator

2014 Mar 01 | Sat

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Split-SAR ADCs: Improved Linearity with Power and Speed Optimization

2014 Feb 01 | Sat

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Split-SAR ADCs: Improved Linearity With Power and Speed Optimization

2014 Feb 01 | Sat

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A Time-Inteleaved Piplined-SAR Analog to Digital Converter with Low Power Consumption

2014 Jan 08 | Wed

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Delay Generator

2014 Jan 08 | Wed

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Cascade Analog to Digital Converting System

2014 Jan 08 | Wed

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Delay Generator

2014 Jan 08 | Wed

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Creativity Prize for the Final Year Project (A 65nm CMOS High-Speed Low-Power Continuous-Time Sigma-Delta Modulator with VCO-Based Quantizer for WiMAX Application)

2014 Jan 03 | Fri

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