A 12b 180MS/s 0.068mm2 Pipelined-SAR ADC with Merged-residue DAC for Noise Reduction 2017 Jan 26 | Thu ...
A Mixed-Signal Sigma-Delta Interface circuit for Navigation System Applications 2017 Jan 26 | Thu ...
A high resolution multi-bit incremental converter insensitive to DAC mismatch error 2017 Jan 26 | Thu ...
A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations 2017 Jan 01 | Sun ...
A Mixed-Signal Sigma-Delta Interface circuit for Navigation System Applications 2016 Dec 01 | Thu ...
A 10-bit 1GS/s 4-way TI SAR ADC with tap-interpolated FIR filter based time skew calibration 2016 Nov 01 | Tue ...
A 0.011mm2 60dB SNDR 100MS/s Reference Error Calibrated SAR ADC with 3pF Decoupling Capacitance for Reference Voltages 2016 Nov 01 | Tue ...
Seven-bit 700-MS/s Four-Way Time-Interleaved SAR ADC With Partial Vcm-Based Switching 2016 Oct 01 | Sat ...