Data Conversion and Signal Processing

60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration

2018 Jan 26 | Fri

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A 16-mW 1-GS/s With 49.6-dB SNDR TI-SAR ADC for Software-Defined Radio in 65-nm CMOS

2017 Dec 01 | Fri

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A 5-bit 2 GS/s binary-search ADC with charge-steering comparators

2017 Nov 01 | Wed

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A 5.35 mW 10 MHz Bandwidth CT Third-Order ∆∑ Modulator with Single Opamp Achieving 79.6/84.5 dB SNDR/DR in 65 nm CMOS

2017 Nov 01 | Wed

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A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH ΔΣ Modulator With Multirate Opamp Sharing

2017 Oct 01 | Sun

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60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration

2017 Oct 01 | Sun

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A missing-code-detection gain error calibration achieving 63dB SNR for an 11-bit ADC

2017 Sep 01 | Fri

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A 7.8mW 5b 5GS/s Dual-Edges-Triggered Time-Based Flash ADC

2017 Aug 01 | Tue

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A 12b 180MS/s 0.068mm2 with Full-Calibration-Integrated Pipelined-SAR ADC

2017 Jul 01 | Sat

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A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations

2017 Mar 17 | Fri

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