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A 13-bit 60M Split Pipelined ADC with Background Gain and Mismatch Error Calibration

Home/A 13-bit 60M Split Pipelined ADC with Background Gain and Mismatch Error Calibration
2013-11-01T00:00:00+08:002013-11-01|Achievements, Research Group, Data Conversion and Signal Processing, Type, Conference papers and presentations|
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