Yong Chen

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Yong Chen
陳勇 Yong Chen
副教授
Phone: (+853) 8822-4470
Room Number: N21-3015g

Biography

Yong Chen (Nick) received the B.Eng. degree in electronic and information engineering, Communication University of China (CUC), Beijing, China, in 2005, and the Ph.D. in Engineering degree in microelectronics and solid-state electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, China, in 2010.

From 2010 to 2013, he worked as Post-Doctoral Researcher in Institute of Microelectronics, Tsinghua University, Beijing, China. From 2013 to 2016, he was Research Fellow responsible for high-speed (40+Gb/s) wireline communication and Low Energy Electronic Systems (LEES) project under the Singapore-MIT Alliance for Research and Technology (SMART) on RF CMOS transceiver in VIRTUS/EEE, Nanyang Technological University, Singapore. He is now an Associate Professor of the State Key Laboratory of Analog and Mixed-Signal VLSI (AMSV) of University of Macau, Macao, China.

His research interests include integrated circuit designs involving analog/mixed-signal/RF/mm-wave/sub-THz/wireline.

Dr. Chen was the recipient of the “Haixi” (three places across the Straits) postgraduate integrated circuit design competition (Second Prize) in 2009, the co-recipient of the Best Paper Award at the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) in 2019 and the co-recipient of the Macao Science and Technology Invention Award (First Prize) in 2020. His team reported 3 chip inventions at the IEEE International Solid-State Circuits Conference – ISSCC (Chip Olympics): mm-wave PLL (’19) and VCO (’19), and radio-frequency VCO (’21).

Dr. Chen serves as an Associate Editor of IEEE Transaction on Very Large Scale Integration (TVLSI) Systems since 2019, an Associate Editor of IEEE Access since 2019, an Associate Editor of IET Electronics Letters (EL) since 2020, an Editor of International Journal of Circuit Theory and Applications (IJCTA) since 2020 and a Guest Editor of IEEE Transactions on Circuits and Systems II: Express Briefs in 2021. He serves as a Vice-Chair of IEEE Macau CAS Chapter (’19-’21), a Tutorial Chair of ICCS (’20), a conference local organization committee of A-SSCC (’19), a member of IEEE Circuits and Systems Society, Circuits and Systems for Communications (CASCOM) Technical Committee (’20-’21), a member of Technical Program Committee (TPC) of APCCAS (’19-’20), ICTA (’20-’21), NorCAS (’20-’21) and ICSICT (’20), a Review Committee Member of ISCAS (’21), and a TPC Co-Chair of ICCS (’21).

Award and Recognition

  • Top five Associate Editors of IEEE Transaction on Very Large Scale Integration (TVLSI) Systems in 2020

  • Macao Science and Technology Award (First Prize) in 2020

  • Best Paper Award in the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2019), Bangkok, Thailand.

  • “Haixi” (three places across the Straits) postgraduate integrated circuit design competition (Second Prize) in 2009

  1. Pui In Mak, Jun Yin, Yong Chen, Man-Kay Law, R. P. Martins, 技術發明獎一等獎(創建萬物連網關鍵微電子芯片)

    The Science and Technology Development Fund(FDCT)

    Oct-2020
  2. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, Best Paper Award

    IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

    Nov-2019
  1. Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, and Rui P. Martins, A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less Single-Loop PAM-4 Bang-Bang CDR With a Deliberate-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS

    IEEE Journal of Solid-State Circuits

    vol. 57, no. 5, pp. 1358-1371 May-2022
  2. Xiaoteng Zhao, Yong Chen, Pui-In Mak, and Rui P. Martins, A 0.0285-mm2 0.68-pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate FD Pulling off an 8.2-(Gb/s)/µs Acquisition Speed of PAM-4 Input in 28-nm CMOS

    IEEE Journal of Solid-State Circuits

    vol. 57, pp. 546–561 Feb-2022
  3. Hao Guo, Yong Chen, Chaowei Yang, Pui-In Mak, and Rui P. Martins, A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RCLM Tank

    IEEE Transactions on Circuits and Systems I: Regular Papers

    vol. 69, no. 1, pp. 172 - 185 Jan-2022
  4. Hao Guo, Yong Chen, Chaowei Yang, Pui-In Mak, Rui P. Martins , A Millimeter-Wave Single-Core CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RLCM Tank

    IEEE Transactions on Circuits and Systems I

    vol. 69, pp. 172-185 Jan-2022
  5. Selvakumar Mariappan, Jagadheswaran Rajendran, Yong Chen, Pui-In Mak, Rui P. Martins, A 1.7-to-2.7GHz 35-38% PAE Multiband CMOS Power Amplifier Employing a Digitally-Assisted Analog Pre-distorter (DAAPD) Reconfigurable Linearization Technique

    IEEE Transactions on Circuits and Systems II: Express Briefs

    vol. 68, No.11.pp. 3381-3385 Nov-2021
  6. Rui P. Martins; Pui-In Mak; Sai-Weng Sin; Man-Kay Law; Yan Zhu; Yan Lu; Jun Yin; Chi-Hang Chan; Yong Chen; Ka-Fai Un; Mo Huang; Minglei Zhang; Yang Jiang; Wei-Han Yu, Revisiting the Frontiers of Analog and Mixed-Signal Integrated Circuits Architectures and Techniques towards the future Internet of Everything (IoE) Applications

    Foundations and Trends in Integrated Circuits and Systems

    Volume 1, Issue 2-3 Nov-2021
  7. Yiqing. Mao, Tianxiang. Wu, Yong Chen, and Shunli Ma, A 0.2-Terahertz Ceramic Relic Detection System Based on Iterative Threshold Filtering Imaging and Neural Network

    Electronics

    10, 2213. Sep-2021
  8. Yunbo Huang, Yong Chen, Hailong Jiao, Pui-In Mak and Rui P. Martins, A 3.36-GHz Locking-Tuned Type-I Sampling PLL with -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques

    IEEE Transactions on Circuits and Systems II: Express Briefs

    vol. 68, No.9,pp. 3093-3097 Sep-2021
  9. Chen Cai, Xuqiang Zheng, Yong Chen, Danyu Wu, Jian Luan, Jin Wu, Lei Zhou, and Xinyu Liu, A 1.55-to-32-Gb/s Four-Lane Fully-Integrated Transmitter with 3-Tap Feed Forward Equalizer in 28nm CMOS

    Electronics

    2021,10, 1873. Aug-2021
  10. Siyuan Yang, Songyi Li, Jiayan Wu, Yong Chen, and Zhenyu Liu, An accelerated architecture of change-point detection for FMCW radar mutual interference based on FPGA

    International Journal of Circuit Theory and Applications

    2021; 1-14. doi:10.1002/cta.3127 Jul-2021
  11. Tianxiang Wu, Jipeng Wei, Hongquan Liu, Shunli Ma, Yong Chen, and Junyan Ren, A Sub-6G SP32T Single-Chip Switch with Nanosecond Switching Speed for 5G Communication in 0.25-μm GaAs Technology

    Electronics

    10, 1482 Jun-2021
  12. Zunsong Yang, Yong Chen, Pui-In Mak, Rui P. Martins, A 0.003-mm2 440fsRMS-Jitter and -64dBc-Reference-Spur Ring-VCO-Based Type-I PLL Using a Current-Reuse Sampling Phase Detector in 28-nm CMOS

    IEEE Transactions on Circuits and Systems I: Regular Papers

    vol. 68, No.6, pp. 2307-2316 Jun-2021
  13. Jincheng Zhang, Tianxiang Wu, Lihe Nie, Shunli Ma, Yong Chen, and Junyan Ren, A 120-150GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm Psat for Sub-THz Imaging System

    IEEE Access

    vol. 9, pp. 74752-74762 May-2021
  14. Rui P. Martins, Pui-In Mak, Chi-Hang Chan, Jun Yin, Yan Zhu, Yong Chen, Yan Lu, Man-Kay Law, Sai-Weng Sin, Bird’s-eye view of Analog and Mixed-Signal Chips for the 21st Century

    International Journal of Circuit Theory and Applications

    vol. 49,No 3, pp. 746-761 Mar-2021
  15. Lingshan Kong, Yong Chen, Haohong Yu, Chirn Chye Boon, Pui-In Mak and Rui P. Martins, Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique

    IEEE Access

    vol. 9, pp. 35814–35823 Feb-2021
  16. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins , A 5.0-to-6.36GHz Wideband-Harmonic-Shaping VCO Achieving 196.9dBc/Hz Peak FoM and 90-to-180kHz 1/f3 PN Corner Without Harmonic Tuning Feb-2021
  17. Zunsong Yang, Yong Chen, Jia Yuan, Pui-In Mak, and Rui P. Martins, A 3.3-GHz Integer-N Type-II Sub-Sampling PLL Using a BFSK-Suppressed Push-Pull SS-PD and a Fast-Locking FLL Achieving −82.2-dBc REF Spur and −255-dB FOM

    IEEE Transactions on VLSI systems

    vol. 30, pp. 238–242 Feb-2021
  18. Fangzhou Sun, Yushi Zhou, Zhanjun Bai, and Yong Chen, A 190.3-dBc/Hz FoM 16-GHz Rotary Travelling-Wave Oscillator With Reliable Direction Control

    IET Electronics Letters

    vol. 57, no. 5, pp. 209-211 Jan-2021
  19. Xiaoteng Zhao, Yong Chen, Pui-In Mak, R. P. Martins, A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery (BBCDR) Circuit in 28-nm CMOS

    IEEE Transactions on Circuits and Systems I: Regular Papers

    vol. 68, no1, pp. 89-102 Jan-2021
  20. Haohong Yu, Yong Chen, Chirn Chye Boon, Pui In Mak, R. P. Martins, A 0.096-mm2 1-to-20-GHz Triple-Path Noise-Cancelling Common-Gate Common-Source LNA with Complementary pMOS-nMOS Configuration

    IEEE Transactions on Microwave Theory and Techniques

    vol. 68, pp. 144-159 Jan-2020
  21. Zunsong Yang, Yong Chen, Shiheng Yang, Pui In Mak, R. P. Martins, A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector

    IEEE Access

    vol. 8, pp. 2222–2232 Jan-2020
  22. Yong Chen, Pui In Mak, Zunsong Yang, Chirn Chye Boon, R. P. Martins, A 0.0071-mm² 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis

    IEEE Transactions on Circuits and Systems I: Regular Paper

    Vol.66, No.10, pp.3991-4004 Oct-2019
  23. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.0018-mm2 153%-Locking-Range CML-Based Divider-by-2 with Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell

    IEEE Transactions on Circuits and Systems I: Regular Papers

    Vol.66, No. 9, pp 3330-3339 Sep-2019
  24. Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui In Mak, R. P. Martins, Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

    Vol.27, Issue 10, pp.2223-2236 Jun-2019
  25. Yong Chen, Zunsong Yang, Xiaoteng Zhao, Yunbo Huang, A 6.5×7 µm2 0.98-to-1.5 mW Non-Self-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4 to 44 GHz)

    IEEE Solid-State Circuits Letters

    Vol.2, Issue: 5, pp. 37-40 May-2019
  26. Haohong Yu, Yong Chen, Chirn Chye Boon, Chenyang Li, Pui In Mak, R. P. Martins, A 0.044-mm2 0.5-to-7-GHz resistor-plus-source-follower-feedback noise-cancelling LNA achieving a flat NF of 3.3±0.45 dB

    IEEE Transactions on Circuits and Systems - II

    Vol. 66. No.1, pp 71 - 75 Jan-2019
  27. Lingshan Kong, Yong Chen, Chirn Chye Boon, Pui In Mak, R. P. Martins, A wideband inductorless dB-linear automatic-gain control amplifier using a single-branch negative exponential generator for wireline applications

    IEEE Transactions on Circuits and Systems - I

    vol. 65, no. 10, pp. 3196-3206 Oct-2018
  28. Yong Chen, Pui In Mak, Chirn Chye Boon, R. P. Martins, A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin

    IEEE Transactions on Circuits and Systems - I

    vol. 65, no. 9, pp. 3014-3026 Sep-2018
  29. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, A 0.083-mm2 25.2-to-29.5 GHz Multi-LC-Tank Class-F234 VCO with a 189.6-dBc/Hz FOM

    IEEE Solid-State Circuits Letters

    vol. 1, no. 4, pp. 86-89 Apr-2018
  30. Yong Chen, Pui In Mak, Haohong Yu, Chirn Chye Boon, R. P. Martins, An Area-Efficient and Tunable Bandwidth-Extension Technique for a Wideband CMOS Amplifier Handling 50+ Gb/s Signaling

    IEEE Transactions on Microwave Theory and Techniques

    vol. 65, Issue 12, pp. 4960-4975 Dec-2017
  31. Yong Chen, Pui In Mak, Chirn Chye Boon, R. P. Martins, A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS

    IEEE Microwave and Wireless Components Letters

    Vol. 27, Issue: 9, pp. 839-841 Sep-2017
  32. Yong Chen, Pui In Mak, Yan Wang, A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links

    IEEE Transactions on Very Large Scale Integration Systems

    vol. 23, pp. 978-982 May-2015
  33. Yong Chen, Pui In Mak, Li Zhang, Yan Wang, A 0.002-mm2 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver with 59.6% Horizontal Eye Opening at 10-12 BER under 23.3-dB Channel Loss at Nyquist

    IEEE Transactions on Microwave Theory and Techniques

    vol. 62, no. 12, pp. 3107-3117 Dec-2014
  34. Yong Chen, Pui In Mak, Stefano D'Amico, Li Zhang, He Qian, Yan Wang, A Single-Branch Third-Order Pole–Zero Low-Pass Filter With 0.014-mm2 Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth–Power Scalability

    IEEE Transactions on Circuits and Systems – II

    Vol. 60, No. 11, pp. 761-765 Nov-2013
  35. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, 0.013 mm2, kHz-to-GHz-bandwidth, thirdorder all-pole lowpass filter with 0.52-to- 1.11 pW/pole/Hz efficiency

    IET Electronics Letters

    Vol.49, Issue 21, pp 1340-1342 Oct-2013
  36. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, Pre-Emphasis Transmitter (0.007mm2, 8Gbit/s, 0-14dB) with Improved Data Zero-Crossing Accuracy in 65nm CMOS

    IET Electronics Letters

    vol. 49, no. 15, pp. 929-930 Jul-2013
  37. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, A 0.0012mm2, 8mW, Single-to-Differential Converter with <1.1% Data Cross Error and <3.4ps RMS Jitter up to 14Gb/s Data Rate

    IET Electronics Letters

    vol.49, no. 11, p. 692-694 May-2013
  38. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, A Fifth-Order 20-MHz Transistorized- -Ladder LPF With 58.2-dB SFDR, 68- Efficiency, and 0.13- Die Size in 90-nm CMOS

    IEEE Transactions on Circuits and Systems – II

    Vol.60, Issue 1, pp 11-15 Jan-2013
  39. Yong Chen, Pui In Mak, L. Zhang, Y. Wang, A 0.07mm2, 2mW, 75MHz-IF, 4th-Order BPF Using a Source-Follower-Based Resonator in 90nm CMOS

    IET Electronics Letters

    Vol.48, No.10 May-2012
  40. Yong Chen, Pui In Mak, Yumei Zhou, Self-Tracking Charge Pump for Fast-Locking PLL

    IET Electronics Letters

    vol. 46, Issue 11, pp. 755-757 May-2010
  41. Yong Chen, Pui In Mak, Yumei Zhou, Mixed-Integrator Biquad for Continuous-Time Filters

    IET Electronics Letters

    vol. 46, Issue 8, pp. 561-563 Apr-2010
  1. Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, and Rui P. Martins, A Sub-0.25pJ/bit 47.6-to-58.8Gb/s Reference-Less FD-Less Single-Loop PAM-4 Bang-Bang CDR with a Deliberately-Current-Mismatch Frequency Acquisition Technique in 28nm CMOS [Best Student Paper Award – 3rd Place]

    IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp 131-134

    Jun-2021
  2. Xiaoteng Zhao, Yong Chen, Xuqiang Zheng, Pui-In Mak, and Rui P. Martins,, A 0.01mm2 1.2-pJ/bit 6.4-to-8Gb/s Reference-less FD-Less BBCDR Using a Deliberately-Clock-Selected Strobe Point Based on a 2π/3-Interval Phase

    IEEE International Microwave Symposium (IMS), pp 386-389

    Jun-2021
  3. Yunbo Huang, Yong Chen, Pui-In Mak, and Rui P. Martins, A 3.52-GHz Harmonic-Rich-Shaping VCO with Noise Suppression and Circulation Achieving -151-dBc/Hz Phase Noise at 10-MHz Offset

    2021 IEEE International Symposium on Circuits and Systems

    May-2021
  4. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, A 0.082mm2 24.5-to-28.3GHz Multi-LC-Tank Fully-Differential VCO Using Two Separate Single-Turn Inductors and a 1D-Tuning Capacitor Achieving 189.4dBc/Hz FOM and 200±50kHz 1/f3 PN Corner

    IEEE Radio Frequency Integrated Circuits (RFIC) Symposium

    Jun-2020
  5. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS

    IEEE Custom Integrated Circuits Conference (CICC)

    Mar-2020
  6. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS

    IEEE Asia Pacific Conference on Circuits and Systems

    Nov-2019
  7. Zunsong Yang, Yong Chen, Shiheng Yang, Pui In Mak, R. P. Martins, A 25.4-to-29.5GHz 10.2mW Isolated-Sub-Sampling PLL (iSS-PLL) Achieving -252.9dB Jitter-power FOM and -63dBc Reference Spur

    IEEE International Solid-State Circuits Conference (ISSCC)

    pp. 270-272 Feb-2019
  8. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6-dBc/Hz FOM and 130kHz 1/f3 PN Corner

    IEEE International Solid-State Circuits Conference (ISSCC)

    pp. 410-412 Feb-2019
  9. Yong Chen, Pui In Mak, Jiale Yang, Ruifeng Yue, Yan Wang, Comparator with Built-in Reference Voltage Generation and Split-ROM Encoder for a High-Speed Flash ADC

    International Symposium on Signals, Circuits and Systems (ISSCS)

    pp. 1-4 Jul-2015
  10. Yong Chen, Pui In Mak, Yumei Zhou, Hao Ju, Li Zhang, He Qian, Yan Wang, Zhiping Yu, A 6-bit 1.3-GS/s Flash ADC using a Gain-Compensated THA and an Offset-Averaging Preamplifier Array

    in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS)

    pp. 1-4 May-2011
  11. Yong Chen, Pui In Mak, Yumei Zhou, Hao Ju, Li Zhang, He Qian, Yan Wang, Zhiping Yu, A Fast Lock-in PLL Using a Quadratic V-I Self-Tracking Charge Pump and a Replica-Biased Ring VCO

    IEEE International Symposium on Circuits and Systems (ISCAS)

    pp. 1872-1875 May-2011
  12. Yong Chen, Pui In Mak, Yumei Zhou, Source-follower-based bi-quad cell for continuous-time zero-pole type filters

    of IEEE International Symposium on Circuits and Systems (ISCAS)

    pp. 3629-3632 May-2010
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