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Yong Chen

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Yong Chen
陳勇 Yong Chen
Assistant Professor
Current Appointment:
Phone: (+853) 8822-4470
Room Number: N21-3015g

Biography

Yong Chen (Nick) received the B.Eng. degree in electronic and information engineering, Communication University of China (CUC), Beijing, China, in 2005, and the Ph.D. in Engineering degree in microelectronics and solid-state electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, China, in 2010.

From 2010 to 2013, he worked as Post-Doctoral Researcher in Institute of Microelectronics, Tsinghua University, Beijing, China. From 2013 to 2016, he was Research Fellow responsible for high-speed (40+Gb/s) wireline communication and Low Energy Electronic Systems (LEES) project under the Singapore-MIT Alliance for Research and Technology (SMART) on RF CMOS transceiver in VIRTUS/EEE, Nanyang Technological University, Singapore. He is now an Assistant Professor of the State Key Laboratory of Analog and Mixed-Signal VLSI (AMSV) of University of Macau, Macao, China, since March 2016.

His research interests include integrated circuit designs involving analog/mixed-signal/RF/mm-wave/sub-THz/wireline.

Dr. Chen was the recipient of the “Haixi” (three places across the Straits) postgraduate integrated circuit design competition (Second Prize) in 2009, the co-recipient of the Best Paper Award at the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) in 2019 and the co-recipient of the Macao Science and Technology Invention Award (First Prize) in 2020. His team reported 3 chip inventions at the IEEE International Solid-State Circuits Conference – ISSCC (Chip Olympics): mm-wave PLL (’19) and VCO (’19), and radio-frequency VCO (’21).

Dr. Chen serves as an Associate Editor of IEEE Transaction on Very Large Scale Integration (TVLSI) Systems since 2019, an Associate Editor of IEEE Access since 2019, an Associate Editor of IET Electronics Letters (EL) since 2020, an Editor of International Journal of Circuit Theory and Applications (IJCTA) since 2020 and a Guest Editor of IEEE Transactions on Circuits and Systems II: Express Briefs in 2021. He serves as a Vice-Chair of IEEE Macau CAS Chapter (’19-’21), a Tutorial Chair of ICCS (’20), a conference local organization committee of A-SSCC (’19), a member of IEEE Circuits and Systems Society, Circuits and Systems for Communications (CASCOM) Technical Committee (’20-’21), a member of Technical Program Committee (TPC) of APCCAS (’19-’20), ICTA (’20-’21), NorCAS (’20-’21) and ICSICT (’20), a Review Committee Member of ISCAS (’21), and a TPC Co-Chair of ICCS (’21).

Award and Recognition

  • Top five Associate Editors of IEEE Transaction on Very Large Scale Integration (TVLSI) Systems in 2020

  • Macao Science and Technology Award (First Prize) in 2020

  • Best Paper Award in the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2019), Bangkok, Thailand.

  • “Haixi” (three places across the Straits) postgraduate integrated circuit design competition (Second Prize) in 2009

  1. Pui In Mak, Jun Yin, Yong Chen, Man-Kay Law, R. P. Martins, 2020 Macao Science & Technology Award – Technological Invention – 1st Prize (Enabling Internet-of-Everything (IoE) Connectivity with Advanced Electronic Chips)

    The Science and Technology Development Fund(FDCT)

     Oct-2020
  2. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, Best Paper Award

    IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

     Nov-2019
  1. Haohong Yu, Yong Chen, Chirn Chye Boon, Pui In Mak, R. P. Martins, A 0.096-mm2 1-to-20-GHz Triple-Path Noise-Cancelling Common-Gate Common-Source LNA with Complementary pMOS-nMOS Configuration

    IEEE Transactions on Microwave Theory and Techniques

     vol. 68, pp. 144-159 Jan-2020
  2. Zunsong Yang, Yong Chen, Shiheng Yang, Pui In Mak, R. P. Martins, A 10.6-mW 26.4-GHz Dual-Loop Type-II Phase-Locked Loop Using Dynamic Frequency Detector and Phase Detector

    IEEE Access

     vol. 8, pp. 2222–2232 Jan-2020
  3. Yong Chen, Pui In Mak, Zunsong Yang, Chirn Chye Boon, R. P. Martins, A 0.0071-mm² 10.8pspp-Jitter 4 to 10-Gb/s 5-Tap Current-Mode Transmitter Using a Hybrid Delay Line for Sub-1-UI Fractional De-Emphasis

    IEEE Transactions on Circuits and Systems I: Regular Paper

     Vol.66, No.10, pp.3991-4004 Oct-2019
  4. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.0018-mm2 153%-Locking-Range CML-Based Divider-by-2 with Tunable Self-Resonant Frequency Using an Auxiliary Negative-gm Cell

    IEEE Transactions on Circuits and Systems I: Regular Papers

     Vol.66, No. 9, pp 3330-3339 Sep-2019
  5. Xinyi Ge, Yong Chen, Xiaoteng Zhao, Pui In Mak, R. P. Martins, Analysis and Verification of Jitter in Bang-Bang Clock and Data Recovery Circuit With a Second-Order Loop Filter

    IEEE Transactions on Very Large Scale Integration (VLSI) Systems

     Vol.27, Issue 10, pp.2223-2236 Jun-2019
  6. Yong Chen, Zunsong Yang, Xiaoteng Zhao, Yunbo Huang, A 6.5×7 µm2 0.98-to-1.5 mW Non-Self-Oscillation-Mode Frequency Divider-by-2 Achieving a Single-Band Untuned Locking Range of 166.6% (4 to 44 GHz)

    IEEE Solid-State Circuits Letters

     Vol.2, Issue: 5, pp. 37-40 May-2019
  7. Haohong Yu, Yong Chen, Chirn Chye Boon, Chenyang Li, Pui In Mak, R. P. Martins, A 0.044-mm2 0.5-to-7-GHz resistor-plus-source-follower-feedback noise-cancelling LNA achieving a flat NF of 3.3±0.45 dB

    IEEE Transactions on Circuits and Systems - II

     Vol. 66. No.1, pp 71 - 75 Jan-2019
  8. Lingshan Kong, Yong Chen, Chirn Chye Boon, Pui In Mak, R. P. Martins, A wideband inductorless dB-linear automatic-gain control amplifier using a single-branch negative exponential generator for wireline applications

    IEEE Transactions on Circuits and Systems - I

     vol. 65, no. 10, pp. 3196-3206 Oct-2018
  9. Yong Chen, Pui In Mak, Chirn Chye Boon, R. P. Martins, A 36-Gb/s 1.3-mW/Gb/s duobinary-signal transmitter exploiting power-efficient cross-quadrature clocking multiplexers with maximized timing margin

    IEEE Transactions on Circuits and Systems - I

     vol. 65, no. 9, pp. 3014-3026 Sep-2018
  10. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, A 0.083-mm2 25.2-to-29.5 GHz Multi-LC-Tank Class-F234 VCO with a 189.6-dBc/Hz FOM

    IEEE Solid-State Circuits Letters

     vol. 1, no. 4, pp. 86-89 Apr-2018
  11. Yong Chen, Pui In Mak, Haohong Yu, Chirn Chye Boon, R. P. Martins, An Area-Efficient and Tunable Bandwidth-Extension Technique for a Wideband CMOS Amplifier Handling 50+ Gb/s Signaling

    IEEE Transactions on Microwave Theory and Techniques

     vol. 65, Issue 12, pp. 4960-4975 Dec-2017
  12. Yong Chen, Pui In Mak, Chirn Chye Boon, R. P. Martins, A 27-Gb/s Time-Interleaved Duobinary Transmitter Achieving 1.44-mW/Gb/s FOM in 65-nm CMOS

    IEEE Microwave and Wireless Components Letters

     Vol. 27, Issue: 9, pp. 839-841 Sep-2017
  13. Yong Chen, Pui In Mak, Yan Wang, A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links

    IEEE Transactions on Very Large Scale Integration Systems

     vol. 23, pp. 978-982 May-2015
  14. Yong Chen, Pui In Mak, Li Zhang, Yan Wang, A 0.002-mm2 6.4-mW 10-Gb/s Full-Rate Direct DFE Receiver with 59.6% Horizontal Eye Opening at 10-12 BER under 23.3-dB Channel Loss at Nyquist

    IEEE Transactions on Microwave Theory and Techniques

     vol. 62, no. 12, pp. 3107-3117 Dec-2014
  15. Yong Chen, Pui In Mak, Stefano D'Amico, Li Zhang, He Qian, Yan Wang, A Single-Branch Third-Order Pole–Zero Low-Pass Filter With 0.014-mm2 Die Size and 0.8-kHz (1.25-nW) to 0.94-GHz (3.99-mW) Bandwidth–Power Scalability

    IEEE Transactions on Circuits and Systems – II

     Vol. 60, No. 11, pp. 761-765 Nov-2013
  16. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, 0.013 mm2, kHz-to-GHz-bandwidth, thirdorder all-pole lowpass filter with 0.52-to- 1.11 pW/pole/Hz efficiency

    IET Electronics Letters

     Vol.49, Issue 21, pp 1340-1342 Oct-2013
  17. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, Pre-Emphasis Transmitter (0.007mm2, 8Gbit/s, 0-14dB) with Improved Data Zero-Crossing Accuracy in 65nm CMOS

    IET Electronics Letters

     vol. 49, no. 15, pp. 929-930 Jul-2013
  18. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, A 0.0012mm2, 8mW, Single-to-Differential Converter with <1.1% Data Cross Error and <3.4ps RMS Jitter up to 14Gb/s Data Rate

    IET Electronics Letters

     vol.49, no. 11, p. 692-694 May-2013
  19. Yong Chen, Pui In Mak, Li Zhang, He Qian, Yan Wang, A Fifth-Order 20-MHz Transistorized- -Ladder LPF With 58.2-dB SFDR, 68- Efficiency, and 0.13- Die Size in 90-nm CMOS

    IEEE Transactions on Circuits and Systems – II

     Vol.60, Issue 1, pp 11-15 Jan-2013
  20. Yong Chen, Pui In Mak, L. Zhang, Y. Wang, A 0.07mm2, 2mW, 75MHz-IF, 4th-Order BPF Using a Source-Follower-Based Resonator in 90nm CMOS

    IET Electronics Letters

     Vol.48, No.10 May-2012
  21. Yong Chen, Pui In Mak, Yumei Zhou, Self-Tracking Charge Pump for Fast-Locking PLL

    IET Electronics Letters

     vol. 46, Issue 11, pp. 755-757 May-2010
  22. Yong Chen, Pui In Mak, Yumei Zhou, Mixed-Integrator Biquad for Continuous-Time Filters

    IET Electronics Letters

     vol. 46, Issue 8, pp. 561-563 Apr-2010
  1. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, A 0.082mm2 24.5-to-28.3GHz Multi-LC-Tank Fully-Differential VCO Using Two Separate Single-Turn Inductors and a 1D-Tuning Capacitor Achieving 189.4dBc/Hz FOM and 200±50kHz 1/f3 PN Corner

    IEEE Radio Frequency Integrated Circuits (RFIC) Symposium

     Jun-2020
  2. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS

    IEEE Custom Integrated Circuits Conference (CICC)

     Mar-2020
  3. Xiaoteng Zhao, Yong Chen, Pui In Mak, R. P. Martins, A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS

    IEEE Asia Pacific Conference on Circuits and Systems

     Nov-2019
  4. Zunsong Yang, Yong Chen, Shiheng Yang, Pui In Mak, R. P. Martins, A 25.4-to-29.5GHz 10.2mW Isolated-Sub-Sampling PLL (iSS-PLL) Achieving -252.9dB Jitter-power FOM and -63dBc Reference Spur

    IEEE International Solid-State Circuits Conference (ISSCC)

     pp. 270-272 Feb-2019
  5. Hao Guo, Yong Chen, Pui In Mak, R. P. Martins, A 0.08mm2 25.5-to-29.9GHz Multi-Resonant-RLCM-Tank VCO Using a Single-Turn Multi-Tap Inductor and CM-Only Capacitors Achieving 191.6-dBc/Hz FOM and 130kHz 1/f3 PN Corner

    IEEE International Solid-State Circuits Conference (ISSCC)

     pp. 410-412 Feb-2019
  6. Yong Chen, Pui In Mak, Jiale Yang, Ruifeng Yue, Yan Wang, Comparator with Built-in Reference Voltage Generation and Split-ROM Encoder for a High-Speed Flash ADC

    International Symposium on Signals, Circuits and Systems (ISSCS)

     pp. 1-4 Jul-2015
  7. Yong Chen, Pui In Mak, Yumei Zhou, Hao Ju, Li Zhang, He Qian, Yan Wang, Zhiping Yu, A 6-bit 1.3-GS/s Flash ADC using a Gain-Compensated THA and an Offset-Averaging Preamplifier Array

    in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS)

     pp. 1-4 May-2011
  8. Yong Chen, Pui In Mak, Yumei Zhou, Hao Ju, Li Zhang, He Qian, Yan Wang, Zhiping Yu, A Fast Lock-in PLL Using a Quadratic V-I Self-Tracking Charge Pump and a Replica-Biased Ring VCO

    IEEE International Symposium on Circuits and Systems (ISCAS)

     pp. 1872-1875 May-2011
  9. Yong Chen, Pui In Mak, Yumei Zhou, Source-follower-based bi-quad cell for continuous-time zero-pole type filters

    of IEEE International Symposium on Circuits and Systems (ISCAS)

     pp. 3629-3632 May-2010
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