
Biography
Yong Chen (Nick) received the B.Eng. degree in electronic and information engineering, Communication University of China (CUC), Beijing, China, in 2005, and the Ph.D. in Engineering degree in microelectronics and solid-state electronics, Institute of Microelectronics of Chinese Academy of Sciences (IMECAS), Beijing, China, in 2010.
From 2010 to 2013, he worked as Post-Doctoral Researcher in Institute of Microelectronics, Tsinghua University, Beijing, China. From 2013 to 2016, he was Research Fellow responsible for high-speed (40+Gb/s) wireline communication and Low Energy Electronic Systems (LEES) project under the Singapore-MIT Alliance for Research and Technology (SMART) on RF CMOS transceiver in VIRTUS/EEE, Nanyang Technological University, Singapore. He is now an Assistant Professor of the State Key Laboratory of Analog and Mixed-Signal VLSI (AMSV) of University of Macau, Macao, China, since March 2016.
His research interests include integrated circuit designs involving analog/mixed-signal/RF/mm-wave/sub-THz/wireline.
Dr. Chen was the recipient of the “Haixi” (three places across the Straits) postgraduate integrated circuit design competition (Second Prize) in 2009, the co-recipient of the Best Paper Award at the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) in 2019 and the co-recipient of the Macao Science and Technology Invention Award (First Prize) in 2020. His team reported 3 chip inventions at the IEEE International Solid-State Circuits Conference – ISSCC (Chip Olympics): mm-wave PLL (’19) and VCO (’19), and radio-frequency VCO (’21).
Dr. Chen serves as an Associate Editor of IEEE Transaction on Very Large Scale Integration (TVLSI) Systems since 2019, an Associate Editor of IEEE Access since 2019, an Associate Editor of IET Electronics Letters (EL) since 2020, an Editor of International Journal of Circuit Theory and Applications (IJCTA) since 2020 and a Guest Editor of IEEE Transactions on Circuits and Systems II: Express Briefs in 2021. He serves as a Vice-Chair of IEEE Macau CAS Chapter (’19-’21), a Tutorial Chair of ICCS (’20), a conference local organization committee of A-SSCC (’19), a member of IEEE Circuits and Systems Society, Circuits and Systems for Communications (CASCOM) Technical Committee (’20-’21), a member of Technical Program Committee (TPC) of APCCAS (’19-’20), ICTA (’20-’21), NorCAS (’20-’21) and ICSICT (’20), a Review Committee Member of ISCAS (’21), and a TPC Co-Chair of ICCS (’21).
Award and Recognition
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Top five Associate Editors of IEEE Transaction on Very Large Scale Integration (TVLSI) Systems in 2020
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Macao Science and Technology Award (First Prize) in 2020
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Best Paper Award in the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2019), Bangkok, Thailand.
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“Haixi” (three places across the Straits) postgraduate integrated circuit design competition (Second Prize) in 2009
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2020 Macao Science & Technology Award – Technological Invention – 1st Prize (Enabling Internet-of-Everything (IoE) Connectivity with Advanced Electronic Chips)
The Science and Technology Development Fund(FDCT)
Oct-2020 -
Best Paper Award
IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Nov-2019
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A Millimeter-Wave CMOS VCO Featuring a Mode-Ambiguity-Aware Multi-Resonant-RCLM Tank
IEEE Transactions on Circuits and Systems I: Regular Papers
vol. 69, no. 1, pp. 172 - 185 Jan-2022
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A 0.082mm2 24.5-to-28.3GHz Multi-LC-Tank Fully-Differential VCO Using Two Separate Single-Turn Inductors and a 1D-Tuning Capacitor Achieving 189.4dBc/Hz FOM and 200±50kHz 1/f3 PN Corner
IEEE Radio Frequency Integrated Circuits (RFIC) Symposium
Jun-2020 -
A 0.0285mm2 0.68pJ/bit Single-Loop Full-Rate Bang-Bang CDR without Reference and Separate Frequency Detector Achieving an 8.2(Gb/s)/µs Acquisition Speed of PAM-4 data in 28nm CMOS
IEEE Custom Integrated Circuits Conference (CICC)
Mar-2020 -
A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS
IEEE Asia Pacific Conference on Circuits and Systems
Nov-2019 -
A 6-bit 1.3-GS/s Flash ADC using a Gain-Compensated THA and an Offset-Averaging Preamplifier Array
in Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS)
pp. 1-4 May-2011 -
A Fast Lock-in PLL Using a Quadratic V-I Self-Tracking Charge Pump and a Replica-Biased Ring VCO
IEEE International Symposium on Circuits and Systems (ISCAS)
pp. 1872-1875 May-2011