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Mingqiang Guo

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Mingqiang Guo
郭銘強 Mingqiang Guo
助理教授
Phone: (+853) 8822-9125
Room Number: N21-3007d

Academic Qualifications

  • Ph.D. in Electrical and Electronics Engineering, Faculty of Science and Technology, University of Macau, China (2020)
  • M.Sc. in Integrated Circuit Engineering, School of Information Science and Technology, Fudan University, Shanghai, China (2014)
  • B.Sc. in Integrated Circuit Design and Integrated Systems, School of Microelectronics, Xidian University, Xi’an, China (2011)

Professional Experience

  • Assistant Professor, State-Key Lab. of Analog and Mixed-Signal VLSI, University of Macau (Apr. 2022 – Present)
  • Postdoctoral Follow, State-Key Lab. of Analog and Mixed-Signal VLSI, University of Macau (July 2020 – Mar. 2022)

Research

Research Interests

  • High-speed data converters
  • Background calibration techniques for ADCs
  • Analog and mixed-signal CMOS integrated circuits

Professional Services

  • Peer Reviewer of
    • IEEE Journal of Solid-State Circuits (JSSC)
    • IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I)
    • IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II)

  1. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 1.6GS/s 12.2mW 7/8-way Split Time-Interleaved SAR ADC achieving 54.2-dB SNDR with Digital Background Timing Mismatch Calibration

    IEEE Journal of Solid-State Circuits

     vol. 55, Issue 3, pp. 693-705 (invited special issue of CICC) Mar-2020
  2. Jiali Ma, Mingqiang Guo, Sai Weng Sin, R. P. Martins, A 14-Bit Split-Pipeline ADC With Self-Adjusted Opamp-Sharing Duty-Cycle and Bias Current

    IEEE Transactions on Circuits and Systems II: Express Briefs

     Vol.65, No.10, pp 1380 - 1384 Oct-2018
  1. Mingqiang Guo, Sai-Weng Sin, Rui P. Martins, Background Timing-Skew Mismatch Calibration for Time-Interleaved ADCs

    2021 International SoC Design Conference (ISOCC), pp 248-249

     Oct-2021
  2. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 29mW 5GS/s Time-interleaved SAR ADC achieving 48.5dB SNDR With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing

    IEEE Symposium on VLSI Circuits (VLSI)

     Jun-2019
  3. Mingqiang Guo, Jiaji Mao, Sai Weng Sin, Hegong Wei, R. P. Martins, A 1.6GS/s 12.2mW 7/8-way Split Time-interleaved SAR ADC with Digital Background Mismatch Calibration

    IEEE Custom Integrated Circuits Conference (CICC)

     Apr-2019
  4. Jiaji Mao, Mingqiang Guo, Sai Weng Sin, R. P. Martins, A 14-bit Split Pipeline ADC with Self-Adjusted Opamp-Sharing Duty Cycle

    IEEE International Solid-State Circuits Conference – ISSCC 2018

     Ph.D. Student Research Preview - Session 3, Paper No.7 Feb-2018
  5. Mingqiang Guo, Sai Weng Sin, Seng-Pan U, R. P. Martins, Split-based time-interleaved ADC with digital background timing-skew calibration

    2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

     Jun-2017
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