Liang QI - University of Macau | State Key Laboratory of Analog and Mixed-Signal VLSI

獎項 Total:1

Liang Qi, Scientific and Technological R&D Award (Master Student), Macau Science and Technology Award 2016
FDCT
Apr-2016

專利與技術轉移 Total:0

期刊和雜誌 Total:10

Hongjiang Chen, Yuhang Peng, Liang Qi, Biao Wang, Sai-Weng Sin, Rui P. Martins and Mingqiang Guo, A 12-Bit 1-Gs/S 5.1-mW Pipelined ADC Using an Open-Loop Floating Inverter Amplifier with Residue-Dependent Integration Time Compensation
IEEE Journal of Solid-State Circuits
vol. 58, Early Access Nov-2025
Xinyu Qin, Yichen Jin, Mingqiang Guo, Guoxing Wang, Sai-Weng Sin, Maurits Ortmanns, Yong Lian, Liang Qi, Analysis and Design of a Pipelined MASH Continuous-Time Delta-Sigma Modulator With 15.4 MHz-BW and 82.6 dB-SNDR
IEEE Transactions on Circuits and Systems I: Regular Papers
Early Access Aug-2025
Ke Li, Haoyu Gong, Congzhou Xianyu, Zhensheng Li, Liang Qi, Mingqiang Guo, Rui P. Martins, Sai-Weng Sin, A 160-MHz BW 68-dB SNDR 36.2 mW Continuous-Time Pipelined ΔΣ ADC With DAC Image Prefiltering
IEEE Journal of Solid-State Circuits
vol. 60, no. 3, pp. 838-849 Dec-2024
Mingqiang Guo, Liang Qi, Weibing Zhao, Gangjun Xiao, Rui P. Martins and Sai -Weng Sin, A 10b 700 MS/s Single-Channel 1b/Cycle SAR ADC Using a Monotonic-Specific Feedback SAR Logic With Power-Delay-Optimized Unbalanced N/P-MOS Sizing
IEEE Transactions on Circuits and Systems I: Regular Papers
Aug-2023
Mingqiang Guo, Sai -Weng Sin, Liang Qi, Dengke Xu, Guoxing Wang and Rui P. Martins, Background Timing Mismatch Calibration Techniques in High-Speed Time-Interleaved ADCs: A Tutorial Review
IEEE Transactions on Circuits and Systems II: Express Briefs
Mar-2022
Dongyang Jiang; Sai-Weng Sin; Liang Qi; Guoxing Wang; Rui P. Martins, Recent Advances in High-Resolution Hybrid Discrete-Time Noise-Shaping ADCs
IEEE Open Journal of the Solid-State Circuits Society
Vol.1, pp. 129-139 Oct-2021
Dongyang Jiang; Liang Qi; Sai-Weng Sin; Franco Maloberti; Rui P. Martins, A Time-Interleaved 2nd-Order ΔΣ Modulator Achieving 5-MHz Bandwidth and 86.1-dB SNDR Using Digital Feed-Forward Extrapolation
IEEE Journal of Solid-State Circuits
Vol.56, No 8, pp. 2375-2387 Aug-2021
Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, A 76.6dB-SNDR 50MHz-BW 29.2mW Multibit CT Sturdy MASH with DAC Non-Linearity Tolerance
IEEE Journal of Solid-State Circuits
vol. 55, No. 2, pp. 344-355 Mar-2020
Liang Qi, Sai Weng Sin, Seng-Pan U, Franco Maloberti, R. P. Martins, A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH ΔΣ Modulator With Multirate Opamp Sharing
IEEE Transactions on Circuits and Systems I - Regular Papers
Vol. 64 , Issue: 10, pp 2641 - 2654 Oct-2017
Liang Qi, Sai Weng Sin, Seng-Pan U, R. P. Martins, Resolution-enhanced sturdy MASH delta–sigma modulator for wideband low-voltage applications
IET, ELECTRONICS LETTERS, Vol. 51, No. 14, pp. 1061–1063
Jul-2015

會議報告和簡報 Total:11

Baolong Huang, Hongjiang Chen, Jingxiang Wang, Yutao Peng, Zhifei Lu, Xizhu Peng, He Tang, Liang Qi, Yawei Guo, Sai-Weng Sin, Rui P. Martins, and Mingqiang Guo, A 3.4 mW 64.5 dB SNDR 800MS/s Pipelined-SAR/TDC ADC with Parallel Amplification and Quantization
2025 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Nov-2025
Hongjiang Chen, Yuhang Peng, Liang Qi, Biao Wang, Sai-Weng Sin, Rui P. Martins and Mingqiang Guo, A 12-Bit 1-Gs/S 5.1-mW Pipelined ADC Using an Open-Loop Floating Inverter Amplifier with Residue-Dependent Integration Time Compensation
2025 IEEE European Solid-State Electronics Research Conference (ESSERC)
Sep-2025
Haoyu Li, Kaize Zhang, Liang Qi, Sai-Weng Sin, Rui P. Martins and Mingqiang Guo, A PVT-Robust 16GS/s 4×TI Time-Domain ADC with Vernier-Based Multipath Flash TDC Achieving 25.7fJ/c-s FoM in 28nm CMOS
2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
Jun-2025
Haoyu Li, Boyang Wang, Hongjiang Chen, Sai-Weng Sin, Yutao Peng, Xizhu Peng, He Tang, Chao Fan, Liang Qi, Rui P. Martins, Mingqiang Guo, A 12.5GS/s 14.7mW 4×TI Pipelined Hybrid TD-SAR ADC with Residual Time-Voltage Amplification
2025 IEEE Custom Integrated Circuits Conference (CICC)
Apr-2025
Ran Zhang, Ka-Fai Un, Mingqiang Guo, Liang Qi, Dengke Xu, Weibing Zhao, R. P. Martins, Franco Maloberti and Sai-Weng Sin, A Delta-Sigma-Based Computing-In-Memory Macro Targeting Edge Computation
IEEE International Symposium on Circuits and Systems (ISCAS)
May-2024
Ke Li, Xianyu Congzhou, Liang Qi, Mingqiang Guo, Rui P. Martins and Sai-Weng Sin, A 160MHz-BW 68dB-SNDR 30.8mW Continuous-Time Pipeline DSM with Correlative Passive Low-Pass Filters and DAC Image Pre-Filtering
IEEE Custom Integrated Circuits Conference (CICC)
Apr-2024
Mingqiang Guo, Sai -Weng Sin, Liang Qi, Gangjun Xiao and Rui P. Martins, A 10b 700MS/s single-channel 1b/cycle SAR ADC using a monotonic-specific feedback SAR logic with power-delay-optimized unbalanced N/P-MOS sizing
2022 IEEE Custom Integrated Circuits Conference (CICC)
Aug-2023
Liang Qi, Xinyu Qin, Sai-Weng Sin, Chixiao Chen, Fan Ye, Guoyong Shi, Guoxing Wang, Advances in Continuous-time MASH ΔΣ Modulators
2021 IEEE International Conference on ASIC (ASICON)
Oct-2021
Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ΔΣ Modulator with Digital Feedforward Extrapolation in 28nm CMOS
2020 Symposium on VLSI Circuits Digest of Technical Papers
Jun-2020
Jiang DongYang, Liang Qi, Sai Weng Sin, Franco Maloberti, R. P. Martins, A 5MHz-BW, 86.1dB-SNDR 4X Time-Interleaved 2nd-order ÄÓ Modulator with Digital Feedforward Extrapolation in 28nm CMOS
CICC 2020
Mar-2020
Liang Qi, Ankesh Jain, Jiang DongYang, Sai Weng Sin, R. P. Martins, Maurits Ortmanns, A 76.6dB-SNDR 50MHz-BW 29.2mW Noise-Coupling-Assisted CT Sturdy MASH ΔΣ Modulator with 1.5b/4b Quantizers in 28nm CMOS
IEEE International Solid-State Circuits Conference (ISSCC 2019)
pp.336-338 Feb-2019

書籍及書籍章節 Total:0